-
WikiChip
WikiChip
-
Architectures
Popular x86
-
Intel
- Client
- Server
- Big Cores
- Small Cores
-
AMD
Popular ARM
-
ARM
- Server
- Big
- Little
-
Cavium
-
Samsung
-
-
Chips
Popular Families
-
Ampere
-
Apple
-
Cavium
-
HiSilicon
-
MediaTek
-
NXP
-
Qualcomm
-
Renesas
-
Samsung
-
From WikiChip
Revision history of "bitmain/sophon/bm1880"
Diff selection: Mark the radio boxes of the revisions to compare and hit enter or the button at the bottom.
Legend: (cur) = difference with latest revision, (prev) = difference with preceding revision, m = minor edit.
Retrieved from "https://en.wikichip.org/wiki/bitmain/sophon/bm1880"
Facts about "Sophon BM1880 - Bitmain"
core name | Cortex-A53 + and RISC-V + |
core voltage | 0.9 V (9 dV, 90 cV, 900 mV) + |
designer | Bitmain + |
family | Sophon + |
first announced | October 17, 2018 + |
first launched | October 17, 2018 + |
full page name | bitmain/sophon/bm1880 + |
has ecc memory support | false + |
instance of | microprocessor + |
io voltage | 1.8 V (18 dV, 180 cV, 1,800 mV) + and 3.3 V (33 dV, 330 cV, 3,300 mV) + |
isa | RV32I + and ARMv8 + |
isa family | RISC-V + and ARM + |
ldate | 3000 + |
manufacturer | TSMC + |
market segment | Edge Compute + |
max memory | 4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) + |
max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
max memory channels | 2 + |
microarchitecture | Cortex-A53 + and RISC-V + |
model number | BM1880 + |
name | Sophon BM1880 + |
peak integer ops (8-bit) | 2,000,000,000,000 OPS (2,000,000,000 KOPS, 2,000,000 MOPS, 2,000 GOPS, 2 TOPS, 0.002 POPS, 2.0e-6 EOPS, 2.0e-9 ZOPS) + |
supported memory type | DDR4-3200 + |
tdp (typical) | 2.5 W (2,500 mW, 0.00335 hp, 0.0025 kW) + |
technology | CMOS + |