From WikiChip
Revision history of "amd/epyc/9354p"
Diff selection: Mark the radio boxes of the revisions to compare and hit enter or the button at the bottom.
Legend: (cur) = difference with latest revision, (prev) = difference with preceding revision, m = minor edit.
Facts about "EPYC 9354P - AMD"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | EPYC 9354P - AMD#pcie + |
| base frequency | 3,250 MHz (3.25 GHz, 3,250,000 kHz) + |
| clock multiplier | 32.5 + |
| core count | 32 + |
| core family | 25 + |
| core model | 17 + |
| core name | Genoa + |
| core stepping | B1 + |
| cpuid | 0x00A10F11 + |
| designer | AMD + |
| die count | 9 + |
| family | EPYC + |
| first launched | November 10, 2022 + |
| full page name | amd/epyc/9354p + |
| has advanced vector extensions | true + |
| has advanced vector extensions 2 | true + |
| has advanced vector extensions 512 | true + |
| has amd amd-v technology | true + |
| has amd amd-vi technology | true + |
| has amd secure encrypted virtualization technology | true + |
| has amd secure memory encryption technology | true + |
| has amd sensemi technology | true + |
| has amd transparent secure memory encryption technology | true + |
| has ecc memory support | true + |
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology + |
| has locked clock multiplier | true + |
| has simultaneous multithreading | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| instance of | microprocessor + |
| is multi-chip package | true + |
| isa | x86-64 + |
| isa family | x86 + |
| l1$ size | 2,048 KiB (2,097,152 B, 2 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) + |
| l3$ description | 16-way set associative + |
| l3$ size | 256 MiB (262,144 KiB, 268,435,456 B, 0.25 GiB) + |
| ldate | November 10, 2022 + |
| manufacturer | TSMC + |
| market segment | Server + |
| max cpu count | 1 + |
| max memory | 6,291,456 MiB (6,442,450,944 KiB, 6,597,069,766,656 B, 6,144 GiB, 6 TiB) + |
| max memory bandwidth | 429.153 GiB/s (439,453.125 MiB/s, 460.8 GB/s, 460,800 MB/s, 0.419 TiB/s, 0.461 TB/s) + |
| max memory channels | 12 + |
| max sata ports | 32 + |
| max usb ports | 4 + |
| microarchitecture | Zen 4 + |
| model number | 9354P + |
| name | EPYC 9354P + |
| package | SP5 + |
| part number | 100-100000805 + and 100-100000805WOF + |
| process | 5 nm (0.005 μm, 5.0e-6 mm) + and 6 nm (0.006 μm, 6.0e-6 mm) + |
| release price | $ 2,730.00 (€ 2,457.00, £ 2,211.30, ¥ 282,090.90) + |
| release price (tray) | $ 2,730.00 (€ 2,457.00, £ 2,211.30, ¥ 282,090.90) + |
| series | 9004 + |
| smp max ways | 1 + |
| socket | Socket SP5 + |
| supported memory type | DDR5-4800 + |
| tdp | 280 W (280,000 mW, 0.375 hp, 0.28 kW) + |
| tdp down | 240 W (240,000 mW, 0.322 hp, 0.24 kW) + |
| tdp up | 300 W (300,000 mW, 0.402 hp, 0.3 kW) + |
| technology | CMOS + |
| thread count | 64 + |
| turbo frequency | 3,750 MHz (3.75 GHz, 3,750,000 kHz) + |
| turbo frequency (1 core) | 3,800 MHz (3.8 GHz, 3,800,000 kHz) + |
| word size | 64 bit (8 octets, 16 nibbles) + |