Revision history of "cavium/octeon plus/cn5740-600bg1217-sp"

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(cur | prev) 13:29, 29 December 2016‎ ChipIt (talk | contribs)‎ . . (3,901 bytes) (+1,091)‎ . . (undo)
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(cur | prev) 20:42, 28 December 2016‎ ChipIt (talk | contribs)‎ . . (2,335 bytes) (+2,335)‎ . . (Created page with "{{cavium title|CN5740-600 SP}} {{mpu | name = Cavium CN5740-600 SP | no image = | image = Octeon CN57xx.svg | image size = |...")

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	CN5740-600 SP - Cavium#package + and CN5740-600 SP - Cavium#io +
base frequency	600 MHz (0.6 GHz, 600,000 kHz) +
core count	8 +
designer	Cavium +
family	OCTEON Plus +
first announced	June 26, 2007 +
first launched	August 2007 +
full page name	cavium/octeon plus/cn5740-600bg1217-sp +
has ecc memory support	true +
has hardware accelerators for data compression	true +
has hardware accelerators for data decompression	true +
has hardware accelerators for network quality of service processing	true +
has hardware accelerators for tcp packet processing	true +
has hardware raid 5 support	true +
has hardware raid 6 support	true +
instance of	microprocessor +
isa	MIPS64 +
isa family	MIPS +
l1$ size	384 KiB (393,216 B, 0.375 MiB) +
l1d$ size	128 KiB (131,072 B, 0.125 MiB) +
l1i$ size	256 KiB (262,144 B, 0.25 MiB) +
l2$ size	2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldate	August 2007 +
main image	+
manufacturer	TSMC +
market segment	Storage +
max cpu count	1 +
max memory bandwidth	11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels	2 +
max pcie lanes	8 +
microarchitecture	cnMIPS +
model number	CN5740-600 SP +
name	Cavium CN5740-600 SP +
package	FCBGA-1217 +
part number	CN5740-600BG1217-SP +
process	90 nm (0.09 μm, 9.0e-5 mm) +
series	CN57xx +
smp max ways	1 +
supported memory type	DDR2-800 + and 1 +
technology	CMOS +
thread count	8 +
word size	64 bit (8 octets, 16 nibbles) +

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