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Latest revision | Your text | ||
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== Release Dates == | == Release Dates == | ||
[[File:zhaoxin roadmap (2017).png|right|400px]] | [[File:zhaoxin roadmap (2017).png|right|400px]] | ||
− | Development for WuDaoKou started in August 2013. The basic architecture design was completed by June 2014 with basic design done in July 2015. WuDaoKou hardware implementation was completed in April 2016 and [[taped out]] in August 2016. Final verification was done in October 2016 and mass production started in October 2017. The KX-5000 (formerly ZX-D) was announced at Semicon China 2017. The architecture and SKUs were officially unveiled at a conference on December 28, | + | Development for WuDaoKou started in August 2013. The basic architecture design was completed by June 2014 with basic design done in July 2015. WuDaoKou hardware implementation was completed in April 2016 and [[taped out]] in August 2016. Final verification was done in October 2016 and mass production started in October 2017. The KX-5000 (formerly ZX-D) was announced at Semicon China 2017. The architecture and SKUs were officially unveiled at a conference on December 28, 2018. |
[[File:wudaokou timeline.png|500px]] | [[File:wudaokou timeline.png|500px]] | ||
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*** Per core | *** Per core | ||
** L2 Cache | ** L2 Cache | ||
− | *** 4 | + | *** 4 MiB, 8-way set associative |
*** Per quad-core cluster | *** Per quad-core cluster | ||
* System DRAM | * System DRAM |
Facts about "WuDaoKou - Microarchitectures - Zhaoxin"
codename | WuDaoKou + |
core count | 2 +, 4 + and 8 + |
designer | Zhaoxin + |
first launched | December 28, 2017 + |
full page name | zhaoxin/microarchitectures/wudaokou + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | HLMC + and SMIC + |
microarchitecture type | CPU + |
name | WuDaoKou + |
pipeline stages | 18 + |
process | 28 nm (0.028 μm, 2.8e-5 mm) + |