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|designer=Zhaoxin | |designer=Zhaoxin | ||
|manufacturer=HLMC | |manufacturer=HLMC | ||
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|introduction=December 28, 2017 | |introduction=December 28, 2017 | ||
|process=28 nm | |process=28 nm | ||
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|extension 14=TXT | |extension 14=TXT | ||
|extension 15=RDSEED | |extension 15=RDSEED | ||
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|predecessor=Zhangjiang | |predecessor=Zhangjiang | ||
|predecessor link=zhaoxin/microarchitectures/zhangjiang | |predecessor link=zhaoxin/microarchitectures/zhangjiang | ||
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}} | }} | ||
'''WuDaoKou''' is the successor to {{\\|Zhangjiang}}, a [[28 nm]] [[x86]] microarchitecture designed by [[Zhaoxin]] for mainstream laptops, desktops, and servers. | '''WuDaoKou''' is the successor to {{\\|Zhangjiang}}, a [[28 nm]] [[x86]] microarchitecture designed by [[Zhaoxin]] for mainstream laptops, desktops, and servers. | ||
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== Brands == | == Brands == | ||
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== Release Dates == | == Release Dates == | ||
[[File:zhaoxin roadmap (2017).png|right|400px]] | [[File:zhaoxin roadmap (2017).png|right|400px]] | ||
− | Development for WuDaoKou started in August 2013. The basic architecture design was completed by June 2014 with basic | + | Development for WuDaoKou started in August 2013. The basic architecture design was completed by June 2014 with basic designed done in July 2015. WuDaoKou logic design was completed in April 2016 and [[taped out]] in August 2016. Final verification was done in October 2016 and mass production started in October 2017. The architecture and SKUs were officially unveiled at a conference on December 28, 2018. |
[[File:wudaokou timeline.png|500px]] | [[File:wudaokou timeline.png|500px]] | ||
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{{clear}} | {{clear}} | ||
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*** DirectX 11.1 | *** DirectX 11.1 | ||
*** Up to 3 displays | *** Up to 3 displays | ||
− | **** DP | + | **** DP / eDP / HDMI / VGA |
* Core | * Core | ||
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** Pipeline was reduced by 5 stages | ** Pipeline was reduced by 5 stages | ||
** Execution engines were re-balanced | ** Execution engines were re-balanced | ||
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=== Block Diagram === | === Block Diagram === | ||
− | + | {{empty section}} | |
=== Memory Hierarchy === | === Memory Hierarchy === | ||
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*** Per core | *** Per core | ||
** L2 Cache | ** L2 Cache | ||
− | *** 4 | + | *** 4 MiB, 32-way set associative |
*** Per quad-core cluster | *** Per quad-core cluster | ||
* System DRAM | * System DRAM | ||
** 2 Channels | ** 2 Channels | ||
** DDR4, Up to 2400 MT/s | ** DDR4, Up to 2400 MT/s | ||
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== Core == | == Core == | ||
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:[[File:wudaokou pipeline.svg|800px]] | :[[File:wudaokou pipeline.svg|800px]] | ||
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== Sockets/Platform == | == Sockets/Platform == | ||
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== Die == | == Die == | ||
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* [[HLMC]] [[28 nm process]] | * [[HLMC]] [[28 nm process]] | ||
* 187 mm² die size | * 187 mm² die size | ||
* 2,100,000,000 transistors | * 2,100,000,000 transistors | ||
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== All WuDaoKou Processors == | == All WuDaoKou Processors == | ||
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</table> | </table> | ||
{{comp table end}} | {{comp table end}} | ||
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== References == | == References == | ||
* Information was obtained directly from Zhaoxin | * Information was obtained directly from Zhaoxin | ||
* [https://fuse.wikichip.org/news/733/zhaoxin-launches-their-highest-performance-chinese-x86-chips/ Zhaoxin launches their highest-performance Chinese x86 chips] | * [https://fuse.wikichip.org/news/733/zhaoxin-launches-their-highest-performance-chinese-x86-chips/ Zhaoxin launches their highest-performance Chinese x86 chips] |
Facts about "WuDaoKou - Microarchitectures - Zhaoxin"
codename | WuDaoKou + |
core count | 2 +, 4 + and 8 + |
designer | Zhaoxin + |
first launched | December 28, 2017 + |
full page name | zhaoxin/microarchitectures/wudaokou + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | HLMC + and SMIC + |
microarchitecture type | CPU + |
name | WuDaoKou + |
pipeline stages | 18 + |
process | 28 nm (0.028 μm, 2.8e-5 mm) + |