Semiconductor & Computer Engineering
From WikiChip
Editing zhaoxin/microarchitectures/wudaokou
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
| Latest revision | Your text | ||
| Line 5: | Line 5: | ||
|designer=Zhaoxin | |designer=Zhaoxin | ||
|manufacturer=HLMC | |manufacturer=HLMC | ||
| − | |||
|introduction=December 28, 2017 | |introduction=December 28, 2017 | ||
|process=28 nm | |process=28 nm | ||
| Line 15: | Line 14: | ||
|speculative=Yes | |speculative=Yes | ||
|renaming=Yes | |renaming=Yes | ||
| − | |||
|isa=x86-64 | |isa=x86-64 | ||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
|predecessor=Zhangjiang | |predecessor=Zhangjiang | ||
|predecessor link=zhaoxin/microarchitectures/zhangjiang | |predecessor link=zhaoxin/microarchitectures/zhangjiang | ||
| Line 49: | Line 21: | ||
}} | }} | ||
'''WuDaoKou''' is the successor to {{\\|Zhangjiang}}, a [[28 nm]] [[x86]] microarchitecture designed by [[Zhaoxin]] for mainstream laptops, desktops, and servers. | '''WuDaoKou''' is the successor to {{\\|Zhangjiang}}, a [[28 nm]] [[x86]] microarchitecture designed by [[Zhaoxin]] for mainstream laptops, desktops, and servers. | ||
| − | |||
| − | |||
| − | |||
== Brands == | == Brands == | ||
| Line 71: | Line 40: | ||
== Release Dates == | == Release Dates == | ||
[[File:zhaoxin roadmap (2017).png|right|400px]] | [[File:zhaoxin roadmap (2017).png|right|400px]] | ||
| − | Development for WuDaoKou started in August 2013. The basic architecture design was completed by June 2014 with basic | + | Development for WuDaoKou started in August 2013. The basic architecture design was completed by June 2014 with basic designed done in July 2015. WuDaoKou logic design was completed in April 2016 and [[taped out]] in August 2016. Final verification was done in October 2016 and mass production started in October 2017. The architecture and SKUs were officially unveiled at a conference on December 28, 2018. |
[[File:wudaokou timeline.png|500px]] | [[File:wudaokou timeline.png|500px]] | ||
| − | |||
| − | |||
{{clear}} | {{clear}} | ||
| Line 98: | Line 65: | ||
*** DirectX 11.1 | *** DirectX 11.1 | ||
*** Up to 3 displays | *** Up to 3 displays | ||
| − | **** DP | + | **** DP / eDP / HDMI / VGA |
* Core | * Core | ||
| − | |||
** Pipeline was reduced by 5 stages | ** Pipeline was reduced by 5 stages | ||
** Execution engines were re-balanced | ** Execution engines were re-balanced | ||
| Line 116: | Line 82: | ||
=== Block Diagram === | === Block Diagram === | ||
| − | + | {{empty section}} | |
=== Memory Hierarchy === | === Memory Hierarchy === | ||
| Line 127: | Line 93: | ||
*** Per core | *** Per core | ||
** L2 Cache | ** L2 Cache | ||
| − | *** 4 | + | *** 4 MiB, 32-way set associative |
*** Per quad-core cluster | *** Per quad-core cluster | ||
* System DRAM | * System DRAM | ||
** 2 Channels | ** 2 Channels | ||
** DDR4, Up to 2400 MT/s | ** DDR4, Up to 2400 MT/s | ||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
== Sockets/Platform == | == Sockets/Platform == | ||
| Line 170: | Line 119: | ||
== Die == | == Die == | ||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
* [[HLMC]] [[28 nm process]] | * [[HLMC]] [[28 nm process]] | ||
* 187 mm² die size | * 187 mm² die size | ||
* 2,100,000,000 transistors | * 2,100,000,000 transistors | ||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
== All WuDaoKou Processors == | == All WuDaoKou Processors == | ||
| Line 219: | Line 154: | ||
</table> | </table> | ||
{{comp table end}} | {{comp table end}} | ||
| − | |||
| − | |||
| − | |||
== References == | == References == | ||
* Information was obtained directly from Zhaoxin | * Information was obtained directly from Zhaoxin | ||
* [https://fuse.wikichip.org/news/733/zhaoxin-launches-their-highest-performance-chinese-x86-chips/ Zhaoxin launches their highest-performance Chinese x86 chips] | * [https://fuse.wikichip.org/news/733/zhaoxin-launches-their-highest-performance-chinese-x86-chips/ Zhaoxin launches their highest-performance Chinese x86 chips] | ||
Facts about "WuDaoKou - Microarchitectures - Zhaoxin"
| codename | WuDaoKou + |
| core count | 2 +, 4 + and 8 + |
| designer | Zhaoxin + |
| first launched | December 28, 2017 + |
| full page name | zhaoxin/microarchitectures/wudaokou + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | HLMC + and SMIC + |
| microarchitecture type | CPU + |
| name | WuDaoKou + |
| pipeline stages | 18 + |
| process | 28 nm (0.028 μm, 2.8e-5 mm) + |