Editing zhaoxin/kaisheng

{{zhaoxin title|KaisHeng (KH)}}
{{ic family
| title             = KaiXian
| image             = 
| caption           = 
| no image          = Yes
| developer         = Zhaoxin
| manufacturer      = TSMC
| type              = Microprocessors
| first announced   = 2016
| first launched    = 2016
| isa               = x86
| microarch         = WuDaoKou
| microarch 2       = LuJiaZui
| microarch 3       = 
| microarch 4       = 
| word              = 64 bit
| proc              = 28 nm
| proc 2            = 
| tech              = CMOS
| clock min         = 
| clock max         = 
| package           = 
| package 2         = 
| package 3         = 
| socket            = 
| socket 2          = 

| succession       = Yes
| predecessor      = QuadCore
| predecessor link = via_technologies/quadcore
| successor        = 
| successor link   = 
}}
'''KaisHeng''' ('''KH''') is a family of [[x86]] microprocessors developed by [[Zhaoxin]] for the [[Chinese]] market. This family is primarily targeting server and networking devices.
@@ Line 1: / Line 1: @@
 {{zhaoxin title|KaisHeng (KH)}}
 {{ic family
-| title             = KaisHeng
+| title             = KaiXian
 | image             =
 | caption           =
@@ Line 8: / Line 8: @@
 | manufacturer      = TSMC
 | type              = Microprocessors
-| first announced   = 2017
+| first announced   = 2016
-| first launched    = 2018
+| first launched    = 2016
 | isa               = x86
 | microarch         = WuDaoKou
@@ Line 34: / Line 34: @@
 }}
 '''KaisHeng''' ('''KH''') is a family of [[x86]] microprocessors developed by [[Zhaoxin]] for the [[Chinese]] market. This family is primarily targeting server and networking devices.
-== Overview ==
-[[File:zhaoxin kh roadmap.jpg|right|400px]]
-Announced in late [[2017]] and officially launched in early [[2018]], the KH series is primarily designed for general-purpose servers. Those chips are fully SoCs solutions that come with an optional I/O extension chipsets.
-== Models ==
-=== KH-20000 ===
-{{main|zhaoxin/microarchitectures/wudaokou|l1=WuDaoKou microarchitecture}}
-The KH-20000 (KH-20k) series is based on the {{zhaoxin|WuDaoKou|l=arch}} microarchitecture and is fabricated on [[HLMC]]'s [[28 nm process]]. Those parts all include the following common features:
-* '''ISA:''' Everything up to AVX (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, SM3, SM4, and AVX)
-* '''Tech:''' {{intel|VT-x}}/{{intel|EPT}}, {{intel|TXT}}
-* '''Mem:''' Up 64 GiB of dual-channel 2133 MT/s DDR4
-<!-- NOTE:
-           This table is generated automatically from the data in the actual articles.
-           If a microprocessor is missing from the list, an appropriate article for it needs to be
-           created and tagged accordingly.
-           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
--->
-{{comp table start}}
-<table class="comptable sortable tc3">
-{{comp table header|main|4:List of WuDaoKou-based KaisHeng Processors}}
-{{comp table header|cols|Launched|Cores|L2|%Frequency}}
-{{#ask: [[Category:microprocessor models by zhaoxin]] [[microarchitecture::WuDaoKou]] [[series::KH-20000]]
- |?full page name
- |?model number
- |?first launched
- |?core count
- |?l2$ size
- |?base frequency#GHz
- |?max memory#GiB
- |?has ecc memory support
- |format=template
- |template=proc table 3
- |userparam=6
- |mainlabel=-
-}}
-{{comp table count|ask=[[Category:microprocessor models by zhaoxin]] [[microarchitecture::WuDaoKou]] [[series::KH-20000]]}}
-</table>
-{{comp table end}}
-=== KH-30000 ===
-{{main|zhaoxin/microarchitectures/lujiazui|l1=LuJiaZui microarchitecture}}
-The KH-30000 is a planned series of processors based on {{zhaoxin|LuJiaZui|l=arch}} set to be fabricated on [[TSMC]]'s [[16 nm process]].
-=== KH-40000 ===
-The KH-40000 is a planned series of processors set to be fabricated on [[TSMC]]'s [[7 nm process]].
designer	Zhaoxin +
first announced	2017 +
first launched	2018 +
full page name	zhaoxin/kaisheng +
instance of	microprocessor family +
instruction set architecture	x86 +
main designer	Zhaoxin +
manufacturer	TSMC +
microarchitecture	WuDaoKou + and LuJiaZui +
name	KaisHeng +
process	28 nm (0.028 μm, 2.8e-5 mm) +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +