Semiconductor & Computer Engineering
From WikiChip
Editing supercomputers/astra
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
| Latest revision | Your text | ||
| Line 1: | Line 1: | ||
| − | {{sc title|Astra}} | + | {{sc title|Astra}}[[File:astra supercomputer illustration.png|thumb|right|class=wikichip_ogimage|Astra Illustration]] |
| − | + | '''Astra''' is a [[petascale]] [[ARM]] supercomputer designed for [[Sandia National Laboratories]] expeced to be deployed in mid-[[2018]]. This is the first ARM-based supercomputer to exceed 1 [[petaFLOPS]]. | |
| − | |||
| − | |||
| − | |||
| − | | | ||
| − | | | ||
| − | | | ||
| − | | | ||
| − | |||
| − | '''Astra''' is a [[petascale]] [[ARM]] | ||
== History == | == History == | ||
| Line 23: | Line 14: | ||
<tr><th>Processors</th><td>5,184<br>2 x 72 x 36</td><td> </td><th>Type</th><td>[[DDR4]]</td><td>[[NVMe]]</td></tr> | <tr><th>Processors</th><td>5,184<br>2 x 72 x 36</td><td> </td><th>Type</th><td>[[DDR4]]</td><td>[[NVMe]]</td></tr> | ||
<tr><th>Racks</th><td>36</td><td> </td><th>Node</th><td>128 GiB</td><td>?</td></tr> | <tr><th>Racks</th><td>36</td><td> </td><th>Node</th><td>128 GiB</td><td>?</td></tr> | ||
| − | <tr><th>Peak FLOPS</th><td>2.322 petaFLOPS ( | + | <tr><th>Peak FLOPS</th><td>2.322 petaFLOPS (SP)<br>1.161 petaFLOPS (DP)</td><td> </td><th>Astra</th><td>324 TiB</td><td>403 TB</td></tr> |
</table> | </table> | ||
| Line 35: | Line 26: | ||
:[[File:astra 540-port switch.svg|thumb|right|540-port Switch]] | :[[File:astra 540-port switch.svg|thumb|right|540-port Switch]] | ||
| − | + | Servers are linked via Mellanox IB EDR interconnect in a three-level fat tree topology with a 2:1 tapered fat-tree at L1. Astra uses three 540-port switches. Those are formed from 30 level 2 switches that provide 18 ports each (540 in total) with the remaining 18 links going for each of the 18 level 3 switches. The system has a peak Wall power of 1.6 MW. | |
| − | The system has a peak Wall power of 1.6 MW. | ||
{| class="wikitable" | {| class="wikitable" | ||
| Line 46: | Line 36: | ||
| 1,631.5 || 1,440.3 || 1,357.3 || 274.9 | | 1,631.5 || 1,440.3 || 1,357.3 || 274.9 | ||
|} | |} | ||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
=== Compute Rack === | === Compute Rack === | ||
| Line 63: | Line 48: | ||
<tr><th>Processors</th><td>144<br>72 × 2 × CPU</td></tr> | <tr><th>Processors</th><td>144<br>72 × 2 × CPU</td></tr> | ||
<tr><th>Core</th><td>4,032 (16,128 threads)<br>72 × 56 (224 threads)</td></tr> | <tr><th>Core</th><td>4,032 (16,128 threads)<br>72 × 56 (224 threads)</td></tr> | ||
| − | <tr><th>FLOPS (SP)</th><td> | + | <tr><th>FLOPS (SP)</th><td>64.51 TFLOPS<br>72 × 2 × 28 × 16 GFLOPS</td></tr> |
| − | <tr><th>FLOPS (DP)</th><td> | + | <tr><th>FLOPS (DP)</th><td>32.26 TFLOPS<br>72 × 2 × 28 × 8 GFLOPS</td></tr> |
<tr><th>Memory</th><td>9 TiB (DRR4)<br>72 × 2 × 8 × 8 GiB</td></tr> | <tr><th>Memory</th><td>9 TiB (DRR4)<br>72 × 2 × 8 × 8 GiB</td></tr> | ||
<tr><th>Memory BW</th><td>24.57 TB/s<br>72 × 16 × 21.33 GB/s</td></tr> | <tr><th>Memory BW</th><td>24.57 TB/s<br>72 × 16 × 21.33 GB/s</td></tr> | ||
| Line 73: | Line 58: | ||
=== Compute Node === | === Compute Node === | ||
[[File:apollo 70 system.png|right|thumb|Apollo 70]] | [[File:apollo 70 system.png|right|thumb|Apollo 70]] | ||
| − | The basic compute server is the HPE Apollo 70. Those use a highly dense chassis system architecture that fit in just 2U and consist of four dual-socket compute nodes. | + | The basic compute server is the HPE Apollo 70. Those use a highly dense chassis system architecture that fit in just 2U and consist of four dual-socket compute nodes. Each node has two 1,600 W power supplies, 1 Gbps Ethernet management port, and a Mellanox ConnectX-5 EDR link. Each node has a dual-socket [[Cavium]] {{cavium|ThunderX2}} [[ThunderX2 CN9975]] ({{cavium|Vulcan|l=arch}}) processor with 28 cores operating at 2 GHz. For Astra, Sandia is using 28-core parts operating at 2 GHz, likely due to a better performance/power efficiency design point. Each chip supports up to eight channels of DDR4 DIMMs with rates up to 2666 MT/s as well as 56 PCIe 3 lanes. |
| − | |||
| − | |||
| − | |||
| − | Each node has two 1,600 W power supplies, 1 Gbps Ethernet management port, and a Mellanox ConnectX-5 EDR link. Each node has a dual-socket [[Cavium]] {{cavium|ThunderX2}} [[ThunderX2 CN9975]] ({{cavium|Vulcan|l=arch}}) processor with 28 cores operating at 2 GHz. For Astra, Sandia is using 28-core parts operating at 2 GHz, likely due to a better performance/power efficiency design point. Each chip supports up to eight channels of DDR4 DIMMs with rates up to 2666 MT/s as well as 56 PCIe 3 lanes. | ||
:[[File:astra node diagram.svg|600px]] | :[[File:astra node diagram.svg|600px]] | ||
| Line 90: | Line 71: | ||
<tr><th>Processors</th><td>1 × CPU</td><td>2 × CPU</td></tr> | <tr><th>Processors</th><td>1 × CPU</td><td>2 × CPU</td></tr> | ||
<tr><th>Core</th><td>28 (112 threads)</td><td>56 (224 threads)</td></tr> | <tr><th>Core</th><td>28 (112 threads)</td><td>56 (224 threads)</td></tr> | ||
| − | <tr><th>FLOPS (SP)</th><td> | + | <tr><th>FLOPS (SP)</th><td>448 GFLOPS<br>28 × 16 GFLOPS</td><td>896 GFLOPS<br>2 × 28 × 16 GFLOPS</td></tr> |
| − | <tr><th>FLOPS ( | + | <tr><th>FLOPS (SP)</th><td>224 GFLOPS<br>28 × 16 GFLOPS</td><td>448 GFLOPS<br>2 × 28 × 8 GFLOPS</td></tr> |
<tr><th>Memory</th><td>64 GiB (DRR4)<br>8 × 8 GiB</td><td>128 GiB (DRR4)<br>2 × 8 × 8 GiB</td></tr> | <tr><th>Memory</th><td>64 GiB (DRR4)<br>8 × 8 GiB</td><td>128 GiB (DRR4)<br>2 × 8 × 8 GiB</td></tr> | ||
<tr><th>Bandwidth</th><td>170.7 GB/s<br>8 × 21.33 GB/s</td><td>341.33 GB/s<br>16 × 21.33 GB/s</td></tr> | <tr><th>Bandwidth</th><td>170.7 GB/s<br>8 × 21.33 GB/s</td><td>341.33 GB/s<br>16 × 21.33 GB/s</td></tr> | ||
</table> | </table> | ||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
== Bibliography == | == Bibliography == | ||
* SNL (personal communication, August 2018). | * SNL (personal communication, August 2018). | ||
* DOE. (June 18, 2018). "''[https://share-ng.sandia.gov/news/resources/news_releases/arm_supercomputer/ Arm-based supercomputer prototype to be deployed at Sandia National Laboratories]''" [Press Release] | * DOE. (June 18, 2018). "''[https://share-ng.sandia.gov/news/resources/news_releases/arm_supercomputer/ Arm-based supercomputer prototype to be deployed at Sandia National Laboratories]''" [Press Release] | ||
| − | * Kevin Pedretti, Jim H. Laros III, Si Hammond. (June 28, 2018) | + | * Kevin Pedretti, Jim H. Laros III, Si Hammond. (June 28, 2018). "''Vanguard Astra: Maturing the ARM Software Ecosystem for U.S. DOE/ASC Supercomputing''" |
| − | + | ||
[[category:supercomputers]] | [[category:supercomputers]] | ||
Facts about "Astra - Supercomputers"
| designer | Cavium + |
| introductory date | 2018 + |
| main image |  + |
| name | Astra + |
| operator | Sandia National Laboratories + |
| peak flops (double-precision) | 2.322e+15 FLOPS (2,322,000,000,000 KFLOPS, 2,322,000,000 MFLOPS, 2,322,000 GFLOPS, 2,322 TFLOPS, 2.322 PFLOPS, 0.00232 EFLOPS, 2.322e-6 ZFLOPS) + |
| sponsor | United States Department of Energy (DOE) + |
