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− | {{sc title|Astra}} | + | {{sc title|Astra}}[[File:astra supercomputer illustration.png|thumb|right|class=wikichip_ogimage|Astra Illustration]] |
− | + | '''Astra''' is a [[petascale]] [[ARM]] supercomputer designed for [[Sandia National Laboratories]] expeced to be deployed in mid-[[2018]]. This is the first ARM-based supercomputer to exceed 1 [[petaFLOPS]]. | |
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− | '''Astra''' is a [[petascale]] [[ARM]] | ||
== History == | == History == | ||
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<tr><th>Processors</th><td>5,184<br>2 x 72 x 36</td><td> </td><th>Type</th><td>[[DDR4]]</td><td>[[NVMe]]</td></tr> | <tr><th>Processors</th><td>5,184<br>2 x 72 x 36</td><td> </td><th>Type</th><td>[[DDR4]]</td><td>[[NVMe]]</td></tr> | ||
<tr><th>Racks</th><td>36</td><td> </td><th>Node</th><td>128 GiB</td><td>?</td></tr> | <tr><th>Racks</th><td>36</td><td> </td><th>Node</th><td>128 GiB</td><td>?</td></tr> | ||
− | <tr><th>Peak FLOPS</th><td>2.322 petaFLOPS ( | + | <tr><th>Peak FLOPS</th><td>2.322 petaFLOPS (SP)<br>1.161 petaFLOPS (DP)</td><td> </td><th>Astra</th><td>324 TiB</td><td>403 TB</td></tr> |
</table> | </table> | ||
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:[[File:astra 540-port switch.svg|thumb|right|540-port Switch]] | :[[File:astra 540-port switch.svg|thumb|right|540-port Switch]] | ||
− | + | Servers are linked via Mellanox IB EDR interconnect in a three-level fat tree topology with a 2:1 tapered fat-tree at L1. Astra uses three 540-port switches. Those are formed from 30 level 2 switches that provide 18 ports each (540 in total) with the remaining 18 links going for each of the 18 level 3 switches. The system has a peak Wall power of 1.6 MW. | |
− | The system has a peak Wall power of 1.6 MW. | ||
{| class="wikitable" | {| class="wikitable" | ||
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| 1,631.5 || 1,440.3 || 1,357.3 || 274.9 | | 1,631.5 || 1,440.3 || 1,357.3 || 274.9 | ||
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=== Compute Rack === | === Compute Rack === | ||
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: [[File:astra racks and cooling (annotated).png|500px]] | : [[File:astra racks and cooling (annotated).png|500px]] | ||
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− | + | A full rack with 72 nodes has 4,032 cores yielding a peak performance of 64.51 [[teraFLOPS]] with over 24.57 TB/s of peak bandwidth. | |
<table class="wikitable"> | <table class="wikitable"> | ||
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<tr><th>Processors</th><td>144<br>72 × 2 × CPU</td></tr> | <tr><th>Processors</th><td>144<br>72 × 2 × CPU</td></tr> | ||
<tr><th>Core</th><td>4,032 (16,128 threads)<br>72 × 56 (224 threads)</td></tr> | <tr><th>Core</th><td>4,032 (16,128 threads)<br>72 × 56 (224 threads)</td></tr> | ||
− | <tr><th>FLOPS (SP)</th><td> | + | <tr><th>FLOPS (SP)</th><td>64.51 TFLOPS<br>72 × 2 × 28 × 16 GFLOPS</td></tr> |
− | <tr><th>FLOPS (DP)</th><td> | + | <tr><th>FLOPS (DP)</th><td>32.26 TFLOPS<br>72 × 2 × 28 × 8 GFLOPS</td></tr> |
<tr><th>Memory</th><td>9 TiB (DRR4)<br>72 × 2 × 8 × 8 GiB</td></tr> | <tr><th>Memory</th><td>9 TiB (DRR4)<br>72 × 2 × 8 × 8 GiB</td></tr> | ||
<tr><th>Memory BW</th><td>24.57 TB/s<br>72 × 16 × 21.33 GB/s</td></tr> | <tr><th>Memory BW</th><td>24.57 TB/s<br>72 × 16 × 21.33 GB/s</td></tr> | ||
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Each compute rack has a projected peak power of 1295.8 kW (1436.0 kW Wall) with a nominal 1217.0 kW of power under [[linpack]]. | Each compute rack has a projected peak power of 1295.8 kW (1436.0 kW Wall) with a nominal 1217.0 kW of power under [[linpack]]. | ||
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=== Compute Node === | === Compute Node === | ||
− | + | {{empty section}} | |
− | + | ==== Socket ==== | |
− | + | {{empty section}} | |
− | + | ==== Full-node ==== | |
− | + | {{empty section}} | |
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== Bibliography == | == Bibliography == | ||
* SNL (personal communication, August 2018). | * SNL (personal communication, August 2018). | ||
* DOE. (June 18, 2018). "''[https://share-ng.sandia.gov/news/resources/news_releases/arm_supercomputer/ Arm-based supercomputer prototype to be deployed at Sandia National Laboratories]''" [Press Release] | * DOE. (June 18, 2018). "''[https://share-ng.sandia.gov/news/resources/news_releases/arm_supercomputer/ Arm-based supercomputer prototype to be deployed at Sandia National Laboratories]''" [Press Release] | ||
− | * Kevin Pedretti, Jim H. Laros III, Si Hammond. (June 28, 2018) | + | * Kevin Pedretti, Jim H. Laros III, Si Hammond. (June 28, 2018). "''Vanguard Astra: Maturing the ARM Software Ecosystem for U.S. DOE/ASC Supercomputing''" |
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[[category:supercomputers]] | [[category:supercomputers]] |
Facts about "Astra - Supercomputers"
designer | Cavium + |
introductory date | 2018 + |
main image | + |
name | Astra + |
operator | Sandia National Laboratories + |
peak flops (double-precision) | 2.322e+15 FLOPS (2,322,000,000,000 KFLOPS, 2,322,000,000 MFLOPS, 2,322,000 GFLOPS, 2,322 TFLOPS, 2.322 PFLOPS, 0.00232 EFLOPS, 2.322e-6 ZFLOPS) + |
sponsor | United States Department of Energy (DOE) + |