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Latest revision | Your text | ||
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{{socionext title|SC2A11}} | {{socionext title|SC2A11}} | ||
− | {{ | + | {{mpu |
|future=Yes | |future=Yes | ||
|name=Socionext SC2A11 | |name=Socionext SC2A11 | ||
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|thread count=24 | |thread count=24 | ||
|max cpus=64 | |max cpus=64 | ||
− | |max memory= | + | |max memory=16 GiB |
|tdp=5 W | |tdp=5 W | ||
}} | }} | ||
− | '''SC2A11''' is a {{arch|64}} [[tetracosa-core]] [[ARM]] system on a chip designed by [[Socionext]] for low-power servers and cloud/[[IoT]] edge computing. This chip, which incorporates 24 ultra-low power {{armh|Cortex-A53|l=arch}} cores, operates at 1 GHz and supports up to | + | '''SC2A11''' is a {{arch|64}} [[tetracosa-core]] [[ARM]] system on a chip designed by [[Socionext]] for low-power servers and cloud/[[IoT]] edge computing. This chip, which incorporates 24 ultra-low power {{armh|Cortex-A53|l=arch}} cores, operates at 1 GHz and supports up to DDR4-2133 EEC memory. |
== Cache == | == Cache == | ||
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|type=DDR4-2133 | |type=DDR4-2133 | ||
|ecc=Yes | |ecc=Yes | ||
− | |||
|channels=2 | |channels=2 | ||
− | |max bandwidth= | + | |max bandwidth=15.89 GiB/s |
|bandwidth schan=15.89 GiB/s | |bandwidth schan=15.89 GiB/s | ||
− | |||
}} | }} | ||
Facts about "SC2A11 - Socionext"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | SC2A11 - Socionext#io + |
base frequency | 1,000 MHz (1 GHz, 1,000,000 kHz) + |
bus type | AMBA + |
core count | 24 + |
core name | Cortex-A53 + |
designer | Socionext + and ARM Holdings + |
first announced | November 14, 2016 + |
first launched | 2017 + |
full page name | socionext/sc2a11 + |
has ecc memory support | true + |
instance of | microprocessor + |
isa | ARMv8 + |
isa family | ARM + |
l1$ size | 1,536 KiB (1,572,864 B, 1.5 MiB) + |
l1d$ description | 4-way set associative + |
l1d$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |
l3$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
ldate | 3000 + |
main image | + |
market segment | Server +, Networking + and IoT + |
max cpu count | 64 + |
max memory | 65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) + |
max memory bandwidth | 31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
max memory channels | 2 + |
max pcie lanes | 4 + |
microarchitecture | Cortex-A53 + |
model number | SC2A11 + |
name | Socionext SC2A11 + |
smp max ways | 64 + |
supported memory type | DDR4-2133 + |
tdp | 5 W (5,000 mW, 0.00671 hp, 0.005 kW) + |
technology | CMOS + |
thread count | 24 + |
word size | 64 bit (8 octets, 16 nibbles) + |