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{{microarchitecture
 
{{microarchitecture
 
|atype=CPU
 
|atype=CPU
−
|name=Cheetah
+
|name=Mongoose 4
 
|designer=Samsung
 
|designer=Samsung
 
|manufacturer=Samsung
 
|manufacturer=Samsung
−
|introduction=2019
+
|introduction=2018
 
|process=8 nm
 
|process=8 nm
−
|cores=4
+
|isa=ARMv8
−
|type=Superscalar
 
−
|type 2=Superpipeline
 
−
|oooe=Yes
 
−
|speculative=Yes
 
−
|renaming=Yes
 
−
|stages=16
 
−
|decode=6-way
 
−
|isa=ARMv8.2
 
−
|l1i=64 KiB
 
−
|l1i per=core
 
−
|l1i desc=4-way set associative
 
−
|l1d=64 KiB
 
−
|l1d per=core
 
−
|l1d desc=8-way set associative
 
−
|l2=512 KiB
 
−
|l2 per=core
 
−
|l2 desc=8-way set associative
 
−
|l3=2 MiB
 
−
|l3 per=cluster
 
−
|l3 desc=16-way set associative
 
 
|predecessor=M3
 
|predecessor=M3
 
|predecessor link=samsung/microarchitectures/m3
 
|predecessor link=samsung/microarchitectures/m3
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|successor link=samsung/microarchitectures/m5
 
|successor link=samsung/microarchitectures/m5
 
}}
 
}}
−
'''Exynos M4''' ('''Cheetah''') is the successor to the {{\\|M3}}, an [[8 nm]] [[ARM]] microarchitecture designed by [[Samsung]] for their consumer electronics.
+
'''Exynos Mongoose 4''' ('''M4''') is the successor to the {{\\|Mongoose 3}}, an [[8 nm]] [[ARM]] microarchitecture designed by [[Samsung]] for their consumer electronics.
  
 
== Process Technology ==
 
== Process Technology ==
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* [[ARMv8.2]] (from [[ARMv8]])
 
* [[ARMv8.2]] (from [[ARMv8]])
 
** Support for full FP16 scalar extension
 
** Support for full FP16 scalar extension
−
** Support for integer dot product extension
+
** Suppot for integer dot product extension
 
* Front end
 
* Front end
 
** Larger [[instruction queue]] (48 entries, up from 40)
 
** Larger [[instruction queue]] (48 entries, up from 40)
 
* Back end
 
* Back end
−
** LSU execution units reorganized
+
** LSU reorganized
 
** Floating-point execution units reorganized
 
** Floating-point execution units reorganized
 
{{expand list}}
 
{{expand list}}
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=== Block Diagram ===
 
=== Block Diagram ===
 
==== Individual Core ====
 
==== Individual Core ====
−
 
 
[[File:mongoose 4 block diagram.svg|900px]]
 
[[File:mongoose 4 block diagram.svg|900px]]
  
 
=== Memory Hierarchy ===
 
=== Memory Hierarchy ===
 
* Cache
 
* Cache
−
** L1I Caches
+
** L1I Cache
 
*** 64 KiB, 4-way set associative
 
*** 64 KiB, 4-way set associative
 
**** 128 B line size
 
**** 128 B line size
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*** 32 B/cycle bandwidth
 
*** 32 B/cycle bandwidth
 
** L3 Cache
 
** L3 Cache
−
*** 2 MiB, 16-way set associative
+
*** 4 MiB, 16-way set associative
 
**** 1 MiB slice/core
 
**** 1 MiB slice/core
 
*** Exlusive of L2
 
*** Exlusive of L2
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*** 80 outstanding transactions
 
*** 80 outstanding transactions
  
−
The M3 TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally, there is a unified L2 TLB (STLB).
+
Mongoose 1 TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally, there is a unified L2 TLB (STLB).
  
 
* TLBs
 
* TLBs
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== Core ==
 
== Core ==
−
The core of the M4 is largely the same as {{\\|M3}}. A number of buffers have been enlarged and some of the execution units have been reorganized.
+
The core of the M4 is largely the same as {{\\|M3}}.
  
 
=== Execution engine ===
 
=== Execution engine ===
 
==== Floating-point cluster ====
 
==== Floating-point cluster ====
−
The execution units on the M4 have been reorganized. In total, three new units were also added  - a second FP square root unit, a second vector multiplication unit, and a new horizontal vector arithmetic unit.
+
{{empty section}}
−
 
 
−
:[[File:m4 fp eu pipes changes.svg|thumb|left|600px|Floating-point pipe changes.]]
 
−
 
 
−
{{clear}}
 
−
 
 
 
==== Memory subsystem ====
 
==== Memory subsystem ====
−
[[File:m4 data cache.svg|thumb|left]]
+
{{empty section}}
−
Samsung also made an enhancement to the M4 memory subsystem. In the M3, there were three AGUs - two dedicated Load [[AGUs]] and a single dedicated Store [[AGU]]. In the M4, Samsung changed one of the dedicated Load [[AGU]]s into a generic AGU capable of handling both loads and stores. In other words, the M4 can now schedule both load and store µOPs on two ports.
 
−
 
 
−
{{clear}}
 
  
−
== All M4 Processors ==
+
== All M3 Processors ==
 
<!-- NOTE:  
 
<!-- NOTE:  
 
           This table is generated automatically from the data in the actual articles.
 
           This table is generated automatically from the data in the actual articles.
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{{comp table start}}
 
{{comp table start}}
 
<table class="comptable sortable tc5 tc6 tc7">
 
<table class="comptable sortable tc5 tc6 tc7">
−
{{comp table header|main|12:List of M4-based Processors}}
+
{{comp table header|main|7:List of M4-based Processors}}
−
{{comp table header|main|5:Main processor|2:Integrated Graphics|{{abbr|TDP}}|2:TDP down|2:TDP up}}
+
{{comp table header|main|5:Main processor|2:Integrated Graphics}}
−
{{comp table header|cols|Family|Launched|Arch|Cores|%Frequency|GPU|%Frequency|P|P|Frequ.|P|Frequ.}}
+
{{comp table header|cols|Family|Launched|Arch|Cores|%Frequency|GPU|%Frequency}}
−
{{#ask: [[Category:microprocessor models by samsung]] [[microarchitecture::M4]]
+
{{#ask: [[Category:microprocessor models by samsung]] [[microarchitecture::Mongoose 4]]
 
  |?full page name
 
  |?full page name
 
  |?model number
 
  |?model number
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  |?integrated gpu
 
  |?integrated gpu
 
  |?integrated gpu base frequency
 
  |?integrated gpu base frequency
−
|?tdp
 
−
|?tdp down
 
−
|?tdp down frequency#GHz
 
−
|?tdp up
 
−
|?tdp up frequency#GHz
 
 
  |format=template
 
  |format=template
 
  |template=proc table 3
 
  |template=proc table 3
−
  |userparam=14
+
  |userparam=9
 
  |mainlabel=-
 
  |mainlabel=-
 
  |valuesep=,
 
  |valuesep=,
 
}}
 
}}
−
{{comp table count|ask=[[Category:microprocessor models by samsung]] [[microarchitecture::M4]]}}
+
{{comp table count|ask=[[Category:microprocessor models by samsung]] [[microarchitecture::Mongoose 4]]}}
 
</table>
 
</table>
 
{{comp table end}}
 
{{comp table end}}

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Facts about "Exynos M4 - Microarchitectures - Samsung"
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codenameCheetah +
core count4 +
designerSamsung +
first launched2019 +
full page namesamsung/microarchitectures/m4 +
instance ofmicroarchitecture +
instruction set architectureARMv8.2 +
manufacturerSamsung +
microarchitecture typeCPU +
nameCheetah +
pipeline stages16 +
process8 nm (0.008 μm, 8.0e-6 mm) +