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{{renesas title|R-Car M3 (SiP)}} | {{renesas title|R-Car M3 (SiP)}} | ||
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Facts about "R-Car M3 (SiP) - Renesas"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | R-Car M3 (SiP) - Renesas#package + |
core count | 7 + |
core name | Cortex-A53 +, Cortex-A57 + and Cortex-R7 + |
core voltage | 0.9 V (9 dV, 90 cV, 900 mV) + |
designer | ARM Holdings + and Renesas + |
family | R-Car + |
first announced | October 19, 2016 + |
first launched | October 2016 + |
full page name | renesas/r-car/m3 (sip) + |
has ecc memory support | false + |
instance of | microprocessor + |
integrated gpu | PowerVR GX6250 + |
integrated gpu designer | Imagination Technologies + |
io voltage | 3.3 V (33 dV, 330 cV, 3,300 mV) + |
isa | ARMv8 + |
isa family | ARM + |
l1$ size | 480 KiB (491,520 B, 0.469 MiB) + |
l1d$ size | 224 KiB (229,376 B, 0.219 MiB) + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ size | 1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) + |
ldate | October 2016 + |
main image | + |
manufacturer | TSMC + |
market segment | Embedded + |
max cpu count | 1 + |
max memory bandwidth | 11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) + |
max memory channels | 2 + |
microarchitecture | Cortex-A53 +, Cortex-A57 + and Cortex-R7 + |
model number | M3 (SiP) + |
name | R-Car M3 (SiP) + |
package | FCBGA-1255 + |
part number | R8J77960 + |
process | 16 nm (0.016 μm, 1.6e-5 mm) + |
series | 3rd Gen + |
smp max ways | 1 + |
supported memory type | LPDDR4-3200 + |
technology | CMOS + |
thread count | 7 + |
word size | 64 bit (8 octets, 16 nibbles) + |