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{{renesas title|R-Car E1}}
 
{{renesas title|R-Car E1}}
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{{chip
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{{mpu
 
|name=R-Car E1
 
|name=R-Car E1
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|image=r-car e1.jpg
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|no image=Yes
 
|designer=Renesas
 
|designer=Renesas
 
|designer 2=ARM Holdings
 
|designer 2=ARM Holdings
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|package module 1={{packages/renesas/fcbga-429}}
 
|package module 1={{packages/renesas/fcbga-429}}
 
}}
 
}}
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'''R-Car E1''' is an entry-level performance embedded SoC for the automotive industry designed by [[Renesas]] and introduced in 2011. The E1 features a single {{armh|Cortex-A9|l=arch}} core operating at 533 MHz. This chip incorporates [[Imagination]]'s {{imgtec|PowerVR SGX531}} [[GPU]] operating at 177 MHz. This SoC supports up to 1 GiB of DDR3-1066 memory.
 
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Announced in mid-2011, Renesas expected the E1 to begin mass production in June 2012 and reach a rate of 100,000 units per month in June 2013.
 
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== Cache ==
 
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{{main|arm holdings/microarchitectures/cortex-a9#Memory_Hierarchy|l1=Cortex-A9 § Cache}}
 
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{{cache size
 
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|l1 cache=64 KiB
 
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|l1i cache=32 KiB
 
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|l1i break=1x32 KiB
 
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|l1i desc=4-way set associative
 
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|l1d cache=32 KiB
 
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|l1d break=1x32 KiB
 
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|l1d desc=4-way set associative
 
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}}
 
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== Memory controller ==
 
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{{memory controller
 
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|type=DDR3-1066
 
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|type 2=DDR2-533
 
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|ecc=No
 
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|max mem=1 GiB
 
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|controllers=1
 
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|channels=1
 
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|width=32 bit
 
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|max bandwidth=1.99 GiB/s
 
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|bandwidth schan=1.99 GiB/s
 
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}}
 
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== Expansions ==
 
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{{expansions
 
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| usb revision      = 2.0
 
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| usb ports          = 2
 
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| usb rate          = 480 Mbps
 
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| uart              = Yes
 
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| uart ports        = 8
 
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| sata revision      = 3.0
 
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| sata ports        = 1
 
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| i2c                = Yes
 
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| i2c ports          = 4
 
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| gp io              = Yes
 
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| jtag              = Yes
 
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}}
 
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* MLB (MOST150) 6-Pin I/F
 
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* 2 x CAN 32 Message Buffers
 
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* MMC
 
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* 3 x SD
 
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== Graphics ==
 
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{{integrated graphics
 
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| gpu                = PowerVR SGX531
 
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| designer            = Imagination Technologies
 
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| execution units    = 1
 
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| max displays        = 2
 
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| frequency          = 177 MHz
 
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| opengl es ver      = 2.0
 
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}}
 
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== Features ==
 
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{{arm features
 
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|thumb=No
 
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|thumb2=Yes
 
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|thumbee=Yes
 
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|vfpv1=No
 
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|vfpv2=No
 
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|vfpv3=Yes
 
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|vfpv3-d16=No
 
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|vfpv3-f16=No
 
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|vfpv4=No
 
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|vfpv4-d16=No
 
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|vfpv5=No
 
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|neon=Yes
 
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|jazelle=Yes
 
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|wmmx=No
 
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|wmmx2=No
 
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}}
 
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== Block Diagram ==
 
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: [[File:rcar e1 block.png|650px]]
 
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: [[File:r-car e1 block.png|650px]]
 

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Facts about "R-Car E1 - Renesas"
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"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
R-Car E1 - Renesas#package +
base frequency533 MHz (0.533 GHz, 533,000 kHz) +
core count1 +
core nameCortex-A9 +
core voltage1.1 V (11 dV, 110 cV, 1,100 mV) +
designerRenesas + and ARM Holdings +
familyR-Car +
first announcedAugust 25, 2011 +
first launchedJune 2012 +
full page namerenesas/r-car/e1 +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuPowerVR SGX531 +
integrated gpu base frequency177 MHz (0.177 GHz, 177,000 KHz) +
integrated gpu designerImagination Technologies +
integrated gpu execution units1 +
io voltage3.3 V (33 dV, 330 cV, 3,300 mV) +
isaARMv7 +
isa familyARM +
l1$ size64 KiB (65,536 B, 0.0625 MiB) +
l1d$ description4-way set associative +
l1d$ size32 KiB (32,768 B, 0.0313 MiB) +
l1i$ description4-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +
ldateJune 2012 +
main imageFile:r-car e1.jpg +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
max memory1,024 MiB (1,048,576 KiB, 1,073,741,824 B, 1 GiB, 9.765625e-4 TiB) +
max memory bandwidth1.99 GiB/s (2,037.76 MiB/s, 2.137 GB/s, 2,136.746 MB/s, 0.00194 TiB/s, 0.00214 TB/s) +
max memory channels1 +
microarchitectureCortex-A9 +
model numberE1 +
nameR-Car E1 +
packageFCBGA-429 +
part numberμPD35004 +
process40 nm (0.04 μm, 4.0e-5 mm) +
release price$ 30.00 (€ 27.00, £ 24.30, ¥ 3,099.90) +
series1st Gen +
smp max ways1 +
supported memory typeDDR3-1066 + and DDR2-533 +
technologyCMOS +
thread count1 +
word size32 bit (4 octets, 8 nibbles) +