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==== Back End ==== | ==== Back End ==== | ||
− | The back-end performs operations [[out-of-order]] for the most part and is in charge of queuing instructions, executing them and retiring them. Dispatch contains a 160-entry [[ReOrder Buffer]] (ROB) and can dispatch up to 4 instructions per cycle. Note that over 210 instructions can be in-flight throughout the entire pipeline. Operand values can be read from Xiaomi's [[physical register file]] and an [[architectural register file]] in order to remove the various dependencies. Registers are only updated from the physical register file to the architectural register file when the corresponding instructions require. The physical register file contains 192 physical [[registers]] supporting up to four parallel instruction reads. Because [[ARM]] has instructions with up to four [[operands]], the register file would need 16 ports to support those simultaneous instructions. To reduce some of the complexity, Phytium chose to reduce the number of ports to 12 where some of the ports are dedicated to each instruction and others are [[multiplexed]]. Phytium explained this decision resulted in a 2.5% reduction in area while adding 0.017% in performance | + | The back-end performs operations [[out-of-order]] for the most part and is in charge of queuing instructions, executing them and retiring them. Dispatch contains a 160-entry [[ReOrder Buffer]] (ROB) and can dispatch up to 4 instructions per cycle. Note that over 210 instructions can be in-flight throughout the entire pipeline. Operand values can be read from Xiaomi's [[physical register file]] and an [[architectural register file]] in order to remove the various dependencies. Registers are only updated from the physical register file to the architectural register file when the corresponding instructions require. The physical register file contains 192 physical [[registers]] supporting up to four parallel instruction reads. Because [[ARM]] has instructions with up to four [[operands]], the register file would need 16 ports to support those simultaneous instructions. To reduce some of the complexity, Phytium chose to reduce the number of ports to 12 where some of the ports are dedicated to each instruction and others are [[multiplexed]]. Phytium explained this decision resulted in a 2.5% reduction in area while adding 0.017% in overhead performance. |
===== Execution Units ===== | ===== Execution Units ===== | ||
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! !! Int !! FP | ! !! Int !! FP | ||
|- | |- | ||
− | ! SPEC_CPU2006_base<br>(Single | + | ! SPEC_CPU2006_base<br>(Single copy) |
|19.2 | |19.2 | ||
|17.8 | |17.8 | ||
|- | |- | ||
− | ! SPEC_CPU2006_rate<br>(64 | + | ! SPEC_CPU2006_rate<br>(64 copies) |
| 672 | | 672 | ||
| 585 | | 585 |
Facts about "Xiaomi - Microarchitectures - Phytium"
codename | Xiaomi + |
designer | Phytium + |
first launched | 2017 + |
full page name | phytium/microarchitectures/xiaomi + |
instance of | microarchitecture + |
instruction set architecture | ARMv8 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Xiaomi + |
process | 28 nm (0.028 μm, 2.8e-5 mm) + |