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| | {{main|phytium/microarchitectures/xiaomi|l1=Xiaomi Core}} | | {{main|phytium/microarchitectures/xiaomi|l1=Xiaomi Core}} |
| | See {{\\|Xiaomi|Xiaomi Core}}. | | See {{\\|Xiaomi|Xiaomi Core}}. |
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| − | == SoC ==
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| − | === Panel Architecture ===
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| − | [[File:xiaomi panel-based data affinity architecture.png|right|450px]]
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| − | Phytium organizes their processors using a grid-layout they call '''Panels''' they call '''Panel-based data affinity architecture'''. Each panel consists of 8 independent [[ARMv8]]-compatible cores. Phytium "Mars" processor consists of 8 such panels for a total of [[64 cores]]. Panels are interconnected with a 2-dimensional mesh network-on-a-chip [[level 2 cache]] with 4 MiB per panel for a total of 32 MiB.
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| − | In addition to the main die, Mars uses an additional '''Cache & Memory chips''' ('''CMC''') auxiliary chips. "Mars" uses 8 such chips connected to the main die providing 16 MiB of [[level 3 cache]] for a total of 128 MiB as well as 8 dual-channel DDR3-1600 [[memory controller]]s for a total maximum bandwidth of 204 GiB/s. Mars also provides two 16-lane PCIe 3.0 interfaces. The chips incorporates ECC and parity protection on all caches, tags, and TLBs.
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| − | ==== Panel ====
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| − | Each Panel consists of 8 cores - each [[ARMv8]]-compatible, supporting AArch32 and AArch64 modes, Exception Levels EL0-EL3, as well as ASIMD-128 operations. Each core has its own inclusive [[L1 cache]] and a shared [[L2 cache]] (4 MiB per panel). Each panel contains two '''Directory Control Units''' ('''DCU''') which are in charge of maintaining directory-based [[cache coherency]] and one routing cell for managing the inter-panel communication.
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| − | On TSMC's [[28 nm process]], a panel is 6,000 µm x 10,600 µm (63.6 mm²).
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| − | {| style="border-spacing: 15px;"
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| − | | [[File:xiaomi panel.png|400px]] || || [[File:xiaomi panel die (28nm).png|300px]]
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| − | |}
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| − | ==== Cache & Memory Chip (CMC) ====
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| − | [[File:xiaomi cmc.png|right|300px]]
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| − | The solve the complexity involved in having more than eight memory controllers on a chip, Xiaomi uses a coupled auxiliary '''Cache & Memory Chip''' ('''CMC''') to scale the bandwidth with computing power. In the case of Phytium "Mars" chip which contains 64 cores on 8 panels, eight CMC chips are used which provides 16 DDR3 controllers (8x2) along with 16 MiB of data L3 cache and 2 MiB of data ECC. Phytium proprietary interface is used between the processor and the CMC chip.
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| − | {|
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| − | | [[File:xiaomi latency.png|600px]] ||
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| − | {| class="wikitable"
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| − | ! Memory access !! Latency(ns)
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| − | |-
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| − | |Local L1 cache hit || ~2
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| − | |-
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| − | |Local L2 cache hit || ~8
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| − | |-
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| − | |Affinitive L2 cache hit || ~20
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| − | |-
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| − | |Affinitive L3 cache hit || ~36
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| − | |-
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| − | |Affinitive DDR access || ~70
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| − | |}
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| − | |}
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| − | * Panel & NoC operates @ 2 GHz
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| − | * CMC operates @ 1.5 GHz
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| − | === Interconnects & Hawk ===
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| − | '''Hawk''' is Pythium cache coherence protocol which implements a distributed directory-based global cache coherency across all the panels. Hawk is a [[MOESI]]-like package-based protocol. The network has a node on each panel called a '''Directory Control Unit''' ('''DCU''') which is responsible for interfacing between the L2 caches in each panel to the CMCs (see [[#Panel_Architecture|§ Panel Architecture]]). Phytium noted that it's optimized for exclusive atomic accesses.
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| − | Xiaomi implements a 2D concentrated mesh architecture on-die connecting each of the panels. Phytium "Mars" chip contains 8 panels which are organized in two rows of four panels each. Switching is relatively low latency with 3 cycles per hop. On average, packets will have around 9 cycles latency from any other panel. This network results in a bandwidth of 384 GiB/s each cell.
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| − | {|
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| − | | [[File:xiaomi 2d network.png|600px]] ||
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| − | {| class="wikitable" style="text-align: center;"
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| − | ! Destination !! Latency
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| − | |-
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| − | | 0 || 3
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| − | |-
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| − | | 1 || 6
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| − | |-
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| − | | 2 || 9
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| − | |-
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| − | | 3 || 12
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| − | |-
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| − | | 4 || 15
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| − | |-
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| − | | 5 || 12
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| − | |-
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| − | | 6 || 9
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| − | |-
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| − | | 7 || 6
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| − | |-
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| − | | Average || 9
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| − | |}
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| − | |}
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| | == Die == | | == Die == |
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| | * Mars is fabricated on [[TSMC]]'s [[28 nm process]] | | * Mars is fabricated on [[TSMC]]'s [[28 nm process]] |
| | * 10 metal layers | | * 10 metal layers |
| − | * 4,800,000,000 transistors
| + | * ~180 million instances |
| − | ** ~180 million instances
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| | * 639.576 mm² die size | | * 639.576 mm² die size |
| − | ** 25.38 mm x 25.2 mm
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| | * FCBGA Package | | * FCBGA Package |
| | ** ~3000 pins | | ** ~3000 pins |
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| | :[[File:xiaomi floor plan.png|class=wikichip_ogimage|700px]] | | :[[File:xiaomi floor plan.png|class=wikichip_ogimage|700px]] |
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| − | == All Mars I Processors ==
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| − | <!-- NOTE:
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| − | This table is generated automatically from the data in the actual articles.
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| − | If a microprocessor is missing from the list, an appropriate article for it needs to be
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| − | created and tagged accordingly.
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| − |
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| − | Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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| − | -->
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| − | {{comp table start}}
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| − | <table class="comptable sortable tc4">
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| − | {{comp table header|main|6:List of Mars I-based Processors}}
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| − | {{comp table header|cols|Launched|Cores|L2|%Frequency|%TDP}}
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| − | {{#ask: [[Category:microprocessor models by phytium]] [[microarchitecture::Mars I]]
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| − | |?full page name
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| − | |?model number
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| − | |?first launched
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| − | |?core count
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| − | |?l2$ size
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| − | |?base frequency#GHz
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| − | |?tdp#W
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| − | |format=template
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| − | |template=proc table 3
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| − | |userparam=7
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| − | |mainlabel=-
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| − | }}
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| − | {{comp table count|ask=[[Category:microprocessor models by phytium]] [[microarchitecture::Mars I]]}}
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| − | </table>
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| − | {{comp table end}}
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| − | == Bibliography ==
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| − | * {{bib|hc|27|Phytium}}
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