From WikiChip
Editing pezy/pezy-scx/pezy-sc
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 38: | Line 38: | ||
== Architecture == | == Architecture == | ||
− | |||
The PEZY-SC microprocessors is made of 4 blocks called "Prefectures". The Prefecture contains 2 MiB of L3$ enclosed by 16 smaller blocks called "Cities". Each City is made of 64 KiB of L2$, a number of special function units, and 4 smaller blocks called "Villages". A village is a block of 4 execution units. For every 2 execution units there is 2 KiB of L1D$. | The PEZY-SC microprocessors is made of 4 blocks called "Prefectures". The Prefecture contains 2 MiB of L3$ enclosed by 16 smaller blocks called "Cities". Each City is made of 64 KiB of L2$, a number of special function units, and 4 smaller blocks called "Villages". A village is a block of 4 execution units. For every 2 execution units there is 2 KiB of L1D$. | ||
[[File:pezy-sc arch.svg|700px]] | [[File:pezy-sc arch.svg|700px]] | ||
+ | |||
+ | === Processor Element (PE) === | ||
+ | {{further|pezy/pezy-scx#Processing Element (PE)|l1=PEZY-SCx § Processing Element (PE)}} | ||
+ | The PE are the individual execution cores. | ||
== Cache == | == Cache == |
Facts about "PEZY-SC - PEZY"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | PEZY-SC - PEZY#pcie + and PEZY-SC - PEZY#package + |
base frequency | 733.33 MHz (0.733 GHz, 733,330 kHz) + |
core count | 1,024 + |
core voltage | 1 V (10 dV, 100 cV, 1,000 mV) + |
designer | PEZY + |
die area | 411.6 mm² (0.638 in², 4.116 cm², 411,600,000 µm²) + |
die length | 19.5 mm (1.95 cm, 0.768 in, 19,500 µm) + |
die width | 21.1 mm (2.11 cm, 0.831 in, 21,100 µm) + |
family | PEZY-SCx + |
first announced | 2013 + |
first launched | September 2014 + |
full page name | pezy/pezy-scx/pezy-sc + |
has ecc memory support | true + |
instance of | microprocessor + |
l1$ size | 64 KiB (65,536 B, 0.0625 MiB) + and 3,072 KiB (3,145,728 B, 3 MiB) + |
l1d$ description | per 2 processor elements + |
l1d$ size | 32 KiB (32,768 B, 0.0313 MiB) + and 1,024 KiB (1,048,576 B, 1 MiB) + |
l1i$ description | per processor element + |
l1i$ size | 32 KiB (32,768 B, 0.0313 MiB) + and 2,048 KiB (2,097,152 B, 2 MiB) + |
l2$ description | per city + |
l2$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + and 0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) + |
l3$ description | per prefecture + |
l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
ldate | September 2014 + |
main image | ![]() |
manufacturer | TSMC + |
market segment | Supercomputer + |
max memory bandwidth | 127.156 GiB/s (130,207.744 MiB/s, 136.533 GB/s, 136,532.715 MB/s, 0.124 TiB/s, 0.137 TB/s) + |
max memory channels | 8 + |
model number | PEZY-SC + |
name | PEZY-SC + |
package | FCBGA-2112 + |
peak flops (double-precision) | 1,501,866,665,984 FLOPS (1,501,866,665.984 KFLOPS, 1,501,866.666 MFLOPS, 1,501.867 GFLOPS, 1.502 TFLOPS, 0.0015 PFLOPS, 1.501867e-6 EFLOPS, 1.501867e-9 ZFLOPS) + |
peak flops (single-precision) | 3,003,733,331,968 FLOPS (3,003,733,331.968 KFLOPS, 3,003,733.332 MFLOPS, 3,003.733 GFLOPS, 3.004 TFLOPS, 0.003 PFLOPS, 3.003733e-6 EFLOPS, 3.003733e-9 ZFLOPS) + |
power dissipation | 100 W (100,000 mW, 0.134 hp, 0.1 kW) + |
power dissipation (average) | 70 W (70,000 mW, 0.0939 hp, 0.07 kW) + |
process | 28 nm (0.028 μm, 2.8e-5 mm) + |
supported memory type | DDR4-2133 + |
technology | CMOS + |
thread count | 8,192 + |
transistor count | 3,730,000,000 + |