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| − | {{nxp title|QorIQ}}
| + | '''QorIQ''' is a family of [[ARM]] and [[POWER]] embedded and networking microprocessors designed and sold by [[NXP]] since [[2008]] as a successor to the {{freescale|PowerQUICC}} family. |
| − | {{ic family
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| − | | title = QorIQ
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| − | | image =
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| − | | caption =
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| − | | no image = Yes
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| − | | developer = Freescale
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| − | | developer 2 = NXP
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| − | | manufacturer = IBM
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| − | | manufacturer 2 = TSMC
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| − | | type = System on Chips
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| − | | first announced = June 16, 2008
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| − | | first launched = June 16, 2008
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| − | | arch = POWER & ARM Communication SoC
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| − | | isa =
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| − | | microarch =
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| − | | microarch 2 =
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| − | | microarch 3 =
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| − | | word = 32 bit
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| − | | word 2 = 64 bit
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| − | | proc = 45 nm
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| − | | proc 2 = 32 nm
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| − | | proc 3 = 20 nm
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| − | | proc 4 = 16 nm
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| − | | tech = CMOS
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| − | | clock min = 533 MHz
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| − | | clock max = 2,000 MHz
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| − | | package =
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| − | | package 2 =
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| − | | package 3 =
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| − | | package 4 =
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| − | | socket =
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| − | | socket 2 =
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| − | | |
| − | | succession = Yes
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| − | | predecessor = PowerQUICC
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| − | | predecessor link = freescale/powerquicc
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| − | | successor =
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| − | | successor link =
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| − | }}
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| − | '''QorIQ''' (pronounced "''Core IQ''") is a family of [[ARM]] and [[POWER]] embedded and networking microprocessors designed and sold by [[NXP]] (formerly [[Freescale]]) since [[2008]] as a successor to the {{freescale|PowerQUICC}} family. | |
| − | | |
| − | == Overview ==
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| − | Introduced in 2008 by [[Freescale]] as a successor to the {{freescale|PowerQUICC}} family, then one of industry's most popular communications processors. Like the PowerQUICC brand, QorIQ spanned the entire range of products from low-power and low-cost to large multi-core designs. Original designs were based on the [[POWER]] architecture. In 2012 Freescale announced the Layerscape series that adopts the [[ARM]] architecture which Freescale/NXP has been using since.
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| − | == Power ==
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| − | {{expand section}}
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| − | | |
| − | === Identification ===
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| − | Only applies to original QorIQ P & T series:
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| − | {{chip identification
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| − | | parts = 6
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| − | | ex 1 = QorIQ
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| − | | ex 2 =
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| − | | ex 3 = P
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| − | | ex 4 = 4
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| − | | ex 5 = 08
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| − | | ex 6 = 0
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| − | | ex 2 1 = QorIQ
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| − | | ex 2 2 =
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| − | | ex 2 3 = P
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| − | | ex 2 4 = 1
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| − | | ex 2 5 = 01
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| − | | ex 2 6 = 3
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| − | | desc 1 = '''Brand Name''' <br><table><tr><td style="width: 50px;">'''QorIQ'''</td><td></td></tr></table>
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| − | | desc 2 =
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| − | | desc 3 = '''[[Technology Node]]'''<br><table><tr><td style="width: 50px;">'''P'''</td><td>[[45 nm process]]</td></tr><tr><td>'''T'''</td><td>[[28 nm process]]</td></tr></table>
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| − | | desc 4 = '''Platform Level'''
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| − | | desc 5 = '''[[Core Count]]'''<br><table><tr><td style="width: 50px;">'''01'''</td><td>[[single-core]]</td></tr><tr><td>'''02'''</td><td>[[dual-core]]</td></tr><tr><td>'''04'''</td><td>[[quad-core]]</td></tr><tr><td>'''08'''</td><td>[[octa-core]]</td></tr></table>
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| − | | desc 6 = '''Iteration/Version'''
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| − | }}
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| − | | |
| − | === P Series ===
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| − | [[File:QorIQ platform levels.png|right|350px]]
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| − | Announced in mid-2008, the QorIQ P-series are [[POWER]]-based microprocessors based on the {{freescale|e500|l=arch}} microarchitecture. Being the first Freescale multicore networking applications based on the [[45 nm process]], those parts offered a migration path for PowerQUICC II Pro and PowerQUICC III processor customers. All chips are fully software compatible with each other and existing PowerQUICC processors with multi-core parts supporting both symmetric and asymmetric multiprocessing.
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| − | | |
| − | ==== P1 ====
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| − | The P1 series are designed for low-power fan-less design designed to succeed previous models (e.g., PowerQUICC II Pro) with higher performance at the same power envelope. All models exhibit a peak power consumption of sub 5 W. P1 parts are designed for the applications such as Ethernet switch controllers, gateways, wireless LAN access points, network printing/storage, and other networking devices with tight thermal constraints.
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| − | | |
| − | <!-- NOTE:
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| − | This table is generated automatically from the data in the actual articles.
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| − | If a microprocessor is missing from the list, an appropriate article for it needs to be
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| − | created and tagged accordingly.
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| − | | |
| − | Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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| − | -->
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| − | {{comp table start}}
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| − | <table class="comptable sortable tc4">
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| − | {{comp table header|main|7:List of QorIQ P1 Processors}}
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| − | {{comp table header|cols|Announced|Cores|Core|%Frequency|L2$|Max Power|Package}}
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| − | {{#ask: [[Category:microprocessor models by freescale]] [[family::QorIQ]] [[series::P1]]
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| − | |?full page name
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| − | |?model number
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| − | |?first announced
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| − | |?core count
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| − | |?core name
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| − | |?base frequency#MHz
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| − | |?l2$ size#KiB
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| − | |?power dissipation#W
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| − | |?package
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| − | |format=template
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| − | |template=proc table 3
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| − | |userparam=9
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| − | |mainlabel=-
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| − | |valuesep=,
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| − | }}
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| − | {{comp table count|ask=[[Category:microprocessor models by freescale]] [[family::QorIQ]] [[series::P1]]}}
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| − | </table>
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| − | {{comp table end}}
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| − | | |
| − | ==== P2 ====
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| − | The P2 series are designed to succeed the PowerQUICC III parts. These parts feature a large cache that may be configured as stashing memory, four Ethernet controllers with QoS features and flow control, DDR2/DDR3 SDRAM Controller with ECC support, four general purpose SerDes lanes that may be configured as either two Serial RapidIO ports, three PCI Express ports and two SGMII ports.
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| − | | |
| − | <!-- NOTE:
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| − | This table is generated automatically from the data in the actual articles.
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| − | If a microprocessor is missing from the list, an appropriate article for it needs to be
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| − | created and tagged accordingly.
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| − | | |
| − | Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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| − | -->
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| − | {{comp table start}}
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| − | <table class="comptable sortable tc4">
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| − | {{comp table header|main|6:List of QorIQ P2 Processors}}
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| − | {{comp table header|cols|Launched|Cores|Core|%Frequency|L2$|Max Power}}
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| − | {{#ask: [[Category:microprocessor models by freescale]] [[family::QorIQ]] [[series::P2]]
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| − | |?full page name
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| − | |?model number
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| − | |?first launched
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| − | |?core count
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| − | |?core name
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| − | |?base frequency#MHz
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| − | |?l2$ size#KiB
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| − | |?power dissipation#W
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| − | |format=template
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| − | |template=proc table 3
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| − | |userparam=8
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| − | |mainlabel=-
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| − | }}
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| − | {{comp table count|ask=[[Category:microprocessor models by freescale]] [[family::QorIQ]] [[series::P2]]}}
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| − | </table>
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| − | {{comp table end}}
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| − | | |
| − | == ARM ==
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| − | {{empty section}}
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| − | | |
| − | == See also ==
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| − | * [[Cavium]] {{cavium|ThunderX}}
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| − | * [[Intel]] {{intel|Atom}}
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