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|l2 per=cluster | |l2 per=cluster | ||
|l2 desc=16-way set associative | |l2 desc=16-way set associative | ||
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'''Denver''' is a CPU microarchitecture from [[Nvidia]] introduced in 2014, capable of executing ARMv8 code natively and with help of dynamic code optimization. Native ARM decoder can issue up to 2 instructions per cycle, and up to 7 micro-operations are started per cycle when dynamic code translation is used. | '''Denver''' is a CPU microarchitecture from [[Nvidia]] introduced in 2014, capable of executing ARMv8 code natively and with help of dynamic code optimization. Native ARM decoder can issue up to 2 instructions per cycle, and up to 7 micro-operations are started per cycle when dynamic code translation is used. | ||
== Architecture == | == Architecture == | ||
− | Denver is 7-wide in-order superscalar. It has ARMv8 hardware decoder | + | Denver is 7-wide in-order superscalar. It has ARMv8 hardware decoder which can generate up to 2 micro-ops per cycle. Also it can execute up to 7 micro-ops per-cycle directly from L1i cache. Denver has 7 execution units: 1 branch, 2 integer (1 has hardware multiply module), 2 FP/NEON (128-bit), 2 Load/Store units. |
− | Denver 2 has dynamic branch prediction with Branch Target Buffer and Global History Buffer | + | Denver 2 has dynamic branch prediction with Branch Target Buffer and Global History Buffer. It also has return stack buffer and indirect predictor. |
Pipeline of Denver 1 has 15 stages, mispredict penalty is 13 cycles. | Pipeline of Denver 1 has 15 stages, mispredict penalty is 13 cycles. | ||
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=== Dynamic Code Optimization === | === Dynamic Code Optimization === | ||
− | For often executed code optimization micro-interrupt can be generated and firmware-based optimizer is started. Using "Dynamic Profile Information" optimizer can translate ARMv8 instructions into optimized microcode sequence and save it into Optimization Cache. Then Denver will execute code directly from Optimization Cache | + | For often executed code optimization micro-interrupt can be generated and firmware-based optimizer is started. Using "Dynamic Profile Information" optimizer can translate ARMv8 instructions into optimized microcode sequence and save it into Optimization Cache. Then Denver will execute code directly from Optimization Cache without using hardware ARMv8 decoder. Several microcode sequences may be chained |
In 2014 Nvidia listed several optimizations for the dynamic code translation: | In 2014 Nvidia listed several optimizations for the dynamic code translation: | ||
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{{cache size | {{cache size | ||
− | |l1 cache= | + | |l1 cache=284 KiB |
|l1i cache=256 KiB | |l1i cache=256 KiB | ||
|l1i break=2x128 KiB | |l1i break=2x128 KiB | ||
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|l1d break=2x64 KiB | |l1d break=2x64 KiB | ||
|l1d desc=4-way set associative | |l1d desc=4-way set associative | ||
+ | |l1d policy= | ||
|l2 cache=2 MiB | |l2 cache=2 MiB | ||
|l2 break=1x2 MiB | |l2 break=1x2 MiB | ||
|l2 desc=16-way set associative | |l2 desc=16-way set associative | ||
+ | |l2 policy= | ||
}} | }} | ||
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== Features == | == Features == | ||
− | {{arm features | + | {{arm features}} |
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== Products == | == Products == | ||
Denver is used in Nvidia's Tegra K1-64 (2014, 28 nm, model T132). It is used in Google's Nexus 9 tablet, produced by HTC. | Denver is used in Nvidia's Tegra K1-64 (2014, 28 nm, model T132). It is used in Google's Nexus 9 tablet, produced by HTC. | ||
− | Denver 2 is used in Nvidia's | + | Denver 2 is used in Nvidia's Terga X2 "Parker" (2016, 16 nm, model T186). Parker SoC has 4 [[Cortex-A57]] cores and two Denver-2 cores. It is used in Nvidia Drive PX2 and Nvidia Jetson TX2. |
== Die == | == Die == |
Facts about "Denver - Microarchitectures - Nvidia"
codename | Denver + |
core count | 2 + |
designer | Nvidia + |
first launched | 2014 + |
full page name | nvidia/microarchitectures/denver + |
instance of | microarchitecture + |
instruction set architecture | ARMv8 + |
l1$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l1d$ description | 4-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Denver + |
process | 28 nm (0.028 μm, 2.8e-5 mm) + and 16 nm (0.016 μm, 1.6e-5 mm) + |