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== Architecture == | == Architecture == | ||
− | Denver is 7-wide in-order superscalar. It has ARMv8 hardware decoder | + | Denver is 7-wide in-order superscalar. It has ARMv8 hardware decoder which can generate up to 2 micro-ops per cycle. Also it can execute up to 7 micro-ops per-cycle directly from L1i cache. Denver has 7 execution units: 1 branch, 2 integer (1 has hardware multiply module), 2 FP/NEON (128-bit), 2 Load/Store units. |
− | Denver 2 has dynamic branch prediction with Branch Target Buffer and Global History Buffer | + | Denver 2 has dynamic branch prediction with Branch Target Buffer and Global History Buffer. It also has return stack buffer and indirect predictor. |
Pipeline of Denver 1 has 15 stages, mispredict penalty is 13 cycles. | Pipeline of Denver 1 has 15 stages, mispredict penalty is 13 cycles. | ||
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=== Dynamic Code Optimization === | === Dynamic Code Optimization === | ||
− | For often executed code optimization micro-interrupt can be generated and firmware-based optimizer is started. Using "Dynamic Profile Information" optimizer can translate ARMv8 instructions into optimized microcode sequence and save it into Optimization Cache. Then Denver will execute code directly from Optimization Cache | + | For often executed code optimization micro-interrupt can be generated and firmware-based optimizer is started. Using "Dynamic Profile Information" optimizer can translate ARMv8 instructions into optimized microcode sequence and save it into Optimization Cache. Then Denver will execute code directly from Optimization Cache without using hardware ARMv8 decoder. Several microcode sequences may be chained |
In 2014 Nvidia listed several optimizations for the dynamic code translation: | In 2014 Nvidia listed several optimizations for the dynamic code translation: |
Facts about "Denver - Microarchitectures - Nvidia"
codename | Denver + |
core count | 2 + |
designer | Nvidia + |
first launched | 2014 + |
full page name | nvidia/microarchitectures/denver + |
instance of | microarchitecture + |
instruction set architecture | ARMv8 + |
l1$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l1d$ description | 4-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Denver + |
process | 28 nm (0.028 μm, 2.8e-5 mm) + and 16 nm (0.016 μm, 1.6e-5 mm) + |