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=== Sparse Data Acceleration === | === Sparse Data Acceleration === | ||
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The SHAVE cores support sparse data operations with the [[load-store unit]] using eight 4-bit fields to generate the address. | The SHAVE cores support sparse data operations with the [[load-store unit]] using eight 4-bit fields to generate the address. | ||
Facts about "SHAVE v2.0 - Microarchitectures - Intel Movidius"
codename | SHAVE v2.0 + |
designer | Movidius + |
first launched | 2011 + |
full page name | movidius/microarchitectures/shave v2.0 + |
instance of | microarchitecture + |
instruction set architecture | SHAVE + and SPARC v8 + |
manufacturer | TSMC + |
name | SHAVE v2.0 + |
phase-out | 2014 + |
process | 65 nm (0.065 μm, 6.5e-5 mm) + |