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=== Sparse Data Acceleration ===
 
=== Sparse Data Acceleration ===
[[File:movidius shave v2.0 sparse data example.png|right|400px]]
 
 
The SHAVE cores support sparse data operations with the [[load-store unit]] using eight 4-bit fields to generate the address.
 
The SHAVE cores support sparse data operations with the [[load-store unit]] using eight 4-bit fields to generate the address.
  

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codenameSHAVE v2.0 +
designerMovidius +
first launched2011 +
full page namemovidius/microarchitectures/shave v2.0 +
instance ofmicroarchitecture +
instruction set architectureSHAVE + and SPARC v8 +
manufacturerTSMC +
nameSHAVE v2.0 +
phase-out2014 +
process65 nm (0.065 μm, 6.5e-5 mm) +