Editing intrinsity/fastmath/fastmath-lp

{{intrinsity title|FastMATH-LP}}
{{mpu
| name                = FastMATH-LP
| no image            = 
| image               = 
| image size          = 
| caption             = 
| designer            = Intrinsity
| manufacturer        = TSMC
| model number        = 
| part number         = 
| part number 1       = 
| market              = Embedded
| first announced     = 2002
| first launched      = 2003
| last order          = 
| last shipment       = 

| family              = FastMATH
| series              = 
| locked              = 
| frequency           = 1,000 MHz
| bus type            = RapidIO
| bus speed           = 500 MHz
| bus rate            = 4 GT/s
| clock multiplier    = 

| microarch           = FashMATH
| platform            = 
| chipset             = 
| core name           = 
| core family         = 
| core model          = 
| core stepping       = 
| process             = 130 nm
| transistors         = 
| technology          = Dynamic CMOS
| die size            = 
| word size           = 32 bit
| core count          = 1
| thread count        = 1
| max cpus            = 
| max memory          = 
| max memory addr     = 

| electrical          = Yes
| power               = 6 W
| v core              = 0.85 V
| v core tolerance    = 
| sdp                 = 
| tdp                 = 
| ctdp down           = 
| ctdp down frequency = 
| ctdp up             = 
| ctdp up frequency   = 
| temp min            = 
| temp max            = 
| tjunc min           = 
| tjunc max           = 
| tcase min           = 
| tcase max           = 
| tstorage min        = 
| tstorage max        = 

| packaging           = Yes
| package 0           = CBGA-670
| package 0 type      = CBGA
| package 0 pins      = 670
| package 0 pitch     = 
| package 0 width     = 
| package 0 length    = 
| package 0 height    = 
| socket 0            = 
| socket 0 type       = 
}}
The '''FastMATH-LP''' was a microprocessor developed by [[Intrinsity]] operating at 1 GHz. The processor incorporates a high-performance [[MIPS]] CPU along with a powerful matrix and vector math unit. This mode was a low-power (LP) version of the normal FastMATH processor, operating at half the speed.
base frequency	1,000 MHz (1 GHz, 1,000,000 kHz) +
bus rate	4,000 MT/s (4 GT/s, 4,000,000 kT/s) +
bus speed	500 MHz (0.5 GHz, 500,000 kHz) +
bus type	RapidIO +
core count	1 +
core voltage	0.85 V (8.5 dV, 85 cV, 850 mV) +
designer	Intrinsity +
family	FastMATH +
first announced	2002 +
first launched	2003 +
full page name	intrinsity/fastmath/fastmath-lp +
has feature	JTAG +
instance of	microprocessor +
l1d$ description	256 blocks × 16 words/block +
l1d$ size	16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description	256 blocks × 16 words/block +
l1i$ size	16 KiB (16,384 B, 0.0156 MiB) +
l2$ description	4-way set associative +
l2$ size	1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldate	2003 +
main image	+
manufacturer	TSMC +
market segment	Embedded +
max memory	1,024 MiB (1,048,576 KiB, 1,073,741,824 B, 1 GiB, 9.765625e-4 TiB) +
microarchitecture	FashMATH +
model number	FastMATH-LP +
name	FastMATH-LP +
power dissipation	6 W (6,000 mW, 0.00805 hp, 0.006 kW) +
process	130 nm (0.13 μm, 1.3e-4 mm) +
technology	Dynamic CMOS +
thread count	1 +
word size	32 bit (4 octets, 8 nibbles) +