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Latest revision | Your text | ||
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{{main|intrinsity/microarchitectures/fastmath#Memory_Hierarchy|l1=FastMATH § Cache}} | {{main|intrinsity/microarchitectures/fastmath#Memory_Hierarchy|l1=FastMATH § Cache}} | ||
{{cache info | {{cache info | ||
− | |l1i cache=16 | + | |l1i cache=16 KB |
− | |l1i break=1x16 | + | |l1i break=1x16 KB |
|l1i desc=256 blocks × 16 words/block | |l1i desc=256 blocks × 16 words/block | ||
− | |l1d cache=16 | + | |l1i extra= |
− | |l1d break=1x16 | + | |l1d cache=16 KB |
+ | |l1d break=1x16 KB | ||
|l1d desc=256 blocks × 16 words/block | |l1d desc=256 blocks × 16 words/block | ||
|l1d extra=write-through or write-back mode | |l1d extra=write-through or write-back mode | ||
− | |l2 cache=1 | + | |l2 cache=1 MB |
− | |l2 break=1x1 | + | |l2 break=1x1 MB |
|l2 desc=4-way set associative | |l2 desc=4-way set associative | ||
− | |l2 extra=(configurable as SRAM in 256 | + | |l2 extra=(configurable as SRAM in 256 KB increments) |
+ | |l3 cache= | ||
+ | |l3 break= | ||
+ | |l3 desc= | ||
+ | |l3 extra= | ||
}} | }} | ||
Facts about "FastMATH-LP - Intrinsity"
base frequency | 1,000 MHz (1 GHz, 1,000,000 kHz) + |
bus rate | 4,000 MT/s (4 GT/s, 4,000,000 kT/s) + |
bus speed | 500 MHz (0.5 GHz, 500,000 kHz) + |
bus type | RapidIO + |
core count | 1 + |
core voltage | 0.85 V (8.5 dV, 85 cV, 850 mV) + |
designer | Intrinsity + |
family | FastMATH + |
first announced | 2002 + |
first launched | 2003 + |
full page name | intrinsity/fastmath/fastmath-lp + |
has feature | JTAG + |
instance of | microprocessor + |
l1d$ description | 256 blocks × 16 words/block + |
l1d$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
l1i$ description | 256 blocks × 16 words/block + |
l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
ldate | 2003 + |
main image | ![]() |
manufacturer | TSMC + |
market segment | Embedded + |
max memory | 1,024 MiB (1,048,576 KiB, 1,073,741,824 B, 1 GiB, 9.765625e-4 TiB) + |
microarchitecture | FashMATH + |
model number | FastMATH-LP + |
name | FastMATH-LP + |
power dissipation | 6 W (6,000 mW, 0.00805 hp, 0.006 kW) + |
process | 130 nm (0.13 μm, 1.3e-4 mm) + |
technology | Dynamic CMOS + |
thread count | 1 + |
word size | 32 bit (4 octets, 8 nibbles) + |