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| clock min = 2.3 GHz | | clock min = 2.3 GHz | ||
| clock max = 4.0 GHz | | clock max = 4.0 GHz | ||
− | | package = FCLGA-2066 | + | | package = FCLGA-2066 |
− | | socket = Socket R4 | + | | socket = Socket R4 |
| succession = Yes | | succession = Yes | ||
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==== W-2200-Series (Cascade Lake) ==== | ==== W-2200-Series (Cascade Lake) ==== | ||
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==== W-3200-Series (Cascade Lake) ==== | ==== W-3200-Series (Cascade Lake) ==== | ||
{{main|intel/microarchitectures/cascade lake|l1=Cascade Lake Microarchitecture}} | {{main|intel/microarchitectures/cascade lake|l1=Cascade Lake Microarchitecture}} | ||
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}} | }} | ||
{{comp table count|ask=[[Category:microprocessor models by intel]] [[core name::Cascade Lake SP]] [[family::Xeon W]]}} | {{comp table count|ask=[[Category:microprocessor models by intel]] [[core name::Cascade Lake SP]] [[family::Xeon W]]}} | ||
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</table> | </table> | ||
{{comp table end}} | {{comp table end}} |
Facts about "Xeon W - Intel"
designer | Intel + |
first announced | August 29, 2017 + |
first launched | August 29, 2017 + |
full page name | intel/xeon w + |
instance of | microprocessor family + |
instruction set architecture | x86-64 + |
main designer | Intel + |
manufacturer | Intel + |
microarchitecture | Skylake + and Cascade Lake + |
name | Xeon W + |
package | FCLGA-2066 or FCLGA3647 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
socket | Socket R4 or Socket P + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |