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{{chip
 
{{chip
 
|name=Xeon W-3225
 
|name=Xeon W-3225
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|image=cascade lake sp (xeon w) (front).png
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|no image=Yes
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
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|s-spec=SRFFB
 
|s-spec=SRFFB
 
|market=Workstation
 
|market=Workstation
−
|first announced=June 3, 2019
 
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|first launched=June 3, 2019
 
 
|release price (tray)=$1,199.00
 
|release price (tray)=$1,199.00
 
|family=Xeon W
 
|family=Xeon W
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|isa family=x86
 
|isa family=x86
 
|microarch=Cascade Lake
 
|microarch=Cascade Lake
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|core name=Cascade Lake SP
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|core name=Cascade Lake W
 
|core stepping=B1
 
|core stepping=B1
 
|process=14 nm
 
|process=14 nm
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|package name 1=intel,fclga_3647
 
|package name 1=intel,fclga_3647
 
}}
 
}}
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'''W-3225''' is a {{arch|64}} [[octa-core]] [[x86]] enterprise performance workstation microprocessor introduced by [[Intel]] in [[2019]]. This processor is fabricated on an enhanced [[14 nm process|14nm++ process]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture. The W-3225 operates at 3.7 GHz with a [[TDP]] of 160 W, a {{intel|turbo boost}} frequency of up to 4.3 GHz and a {{intel|turbo boost max}} of 4.4 GHz. This chip supports up to 1 TiB of hexa-channel DDR4-2666 memory.
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'''W-3225''' is a {{arch|64}} [[octa-core]] [[x86]] enterprise performance workstation microprocessor introduced by [[Intel]] in [[2019]]. This processors, which is fabricated on an enhanced [[14 nm process|14nm++ process]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture, operates at 3.7 GHz with a [[TDP]] of 160 W and a {{intel|turbo boost}} frequency of up to ? GHz.
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{{unknown features}}
  
  
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{{#set:intel turbo boost max technology 3 0 frequency=4.4 GHz}}
 
 
== Cache ==
 
== Cache ==
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{{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}}
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{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
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This processor has a non-default [[level 3 cache]] of 16.5 MiB, an amount usually found in the [[12 cores]] part.
 
 
{{cache size
 
{{cache size
 
|l1 cache=512 KiB
 
|l1 cache=512 KiB
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|l2 desc=16-way set associative
 
|l2 desc=16-way set associative
 
|l2 policy=write-back
 
|l2 policy=write-back
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|l3 cache=16.5 MiB
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|l3 cache=11 MiB
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|l3 break=12x1.375 MiB
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|l3 break=8x1.375 MiB
 
|l3 desc=11-way set associative
 
|l3 desc=11-way set associative
 
|l3 policy=write-back
 
|l3 policy=write-back
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== Memory controller ==
 
== Memory controller ==
 
{{memory controller
 
{{memory controller
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|type=DDR4-2666
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|type=DDR4-2933
 
|ecc=Yes
 
|ecc=Yes
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|max mem=1 TiB
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|max mem=1.5 TiB
 
|controllers=2
 
|controllers=2
 
|channels=6
 
|channels=6
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|max bandwidth=119.21 GiB/s
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|max bandwidth=131.13 GiB/s
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|bandwidth schan=19.87 GiB/s
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|bandwidth schan=21.86 GiB/s
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|bandwidth dchan=39.74 GiB/s
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|bandwidth dchan=43.71 GiB/s
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|bandwidth qchan=79.47 GiB/s
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|bandwidth qchan=87.42 GiB/s
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|bandwidth hchan=119.21 GiB/s
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|bandwidth hchan=131.13 GiB/s
 
}}
 
}}
  
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|type=PCIe
 
|type=PCIe
 
|pcie revision=3.0
 
|pcie revision=3.0
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|pcie lanes=64
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|pcie lanes=48
 
|pcie config=x16
 
|pcie config=x16
 
|pcie config 2=x8
 
|pcie config 2=x8
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|avx512vbmi=No
 
|avx512vbmi=No
 
|avx5124fmaps=No
 
|avx5124fmaps=No
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|avx512vnni=Yes
 
 
|avx5124vnniw=No
 
|avx5124vnniw=No
 
|avx512vpopcntdq=No
 
|avx512vpopcntdq=No
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|clmul=Yes
 
|clmul=Yes
 
|f16c=Yes
 
|f16c=Yes
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|bfloat16=No
 
 
|tbt1=No
 
|tbt1=No
 
|tbt2=Yes
 
|tbt2=Yes
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|tbmt3=Yes
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|tbmt3=No
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|tvb=No
 
 
|bpt=No
 
|bpt=No
 
|eist=Yes
 
|eist=Yes
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|osguard=Yes
 
|osguard=Yes
 
|intqat=No
 
|intqat=No
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|dlboost=Yes
 
 
|3dnow=No
 
|3dnow=No
 
|e3dnow=No
 
|e3dnow=No
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|sensemi=No
 
|sensemi=No
 
|xfr=No
 
|xfr=No
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|xfr2=No
 
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|mxfr=No
 
−
|amdpb=No
 
−
|amdpb2=No
 
−
|amdpbod=No
 
 
}}
 
}}
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−
== Documents ==
 
−
* [[:File:w-3200-pb.pdf|Xeon W-3200 Series Product Brief]]
 

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Facts about "Xeon W-3225 - Intel"
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Xeon W-3225 - Intel#pcie +
base frequency3,700 MHz (3.7 GHz, 3,700,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
clock multiplier37 +
core count8 +
core nameCascade Lake SP +
core steppingB1 +
designerIntel +
familyXeon W +
first announcedJune 3, 2019 +
first launchedJune 3, 2019 +
full page nameintel/xeon w/w-3225 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Encryption Standard Instruction Set Extension +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Deep Learning Boost +, Enhanced SpeedStep Technology +, Extended Page Tables +, Hyper-Threading Technology +, Identity Protection Technology +, Intel VT-d +, Intel VT-x +, Intel vPro Technology +, Memory Protection Extensions +, OS Guard +, Secure Key Technology +, Speed Shift Technology +, Transactional Synchronization Extensions +, Trusted Execution Technology +, Turbo Boost Max Technology 3.0 + and Turbo Boost Technology 2.0 +
has intel deep learning boosttrue +
has intel enhanced speedstep technologytrue +
has intel identity protection technology supporttrue +
has intel secure key technologytrue +
has intel speed shift technologytrue +
has intel supervisor mode execution protectiontrue +
has intel trusted execution technologytrue +
has intel turbo boost max technology 3 0true +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
intel turbo boost max technology 3 0 frequency4,400 MHz (4.4 GHz, 4,400,000 kHz) +
isax86-64 +
isa familyx86 +
l1$ size512 KiB (524,288 B, 0.5 MiB) +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description8-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description16-way set associative +
l2$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description11-way set associative +
l3$ size16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) +
ldateJune 3, 2019 +
main imageFile:cascade lake sp (xeon w) (front).png +
manufacturerIntel +
market segmentWorkstation +
max cpu count1 +
max memory1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
max memory bandwidth119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels6 +
microarchitectureCascade Lake +
model numberW-3225 +
nameXeon W-3225 +
number of avx-512 execution units2 +
packageFCLGA-3647 +
part numberCD8069504152705 +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 1,199.00 (€ 1,079.10, £ 971.19, ¥ 123,892.67) +
release price (tray)$ 1,199.00 (€ 1,079.10, £ 971.19, ¥ 123,892.67) +
s-specSRFFB +
seriesW-3200 +
smp max ways1 +
socketLGA-3647 + and Socket P +
supported memory typeDDR4-2666 +
tdp160 W (160,000 mW, 0.215 hp, 0.16 kW) +
technologyCMOS +
thread count16 +
turbo frequency (1 core)4,300 MHz (4.3 GHz, 4,300,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensionstrue +