From WikiChip
Editing intel/xeon w/w-3223

Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.

This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.

Latest revision Your text
Line 1: Line 1:
 
{{intel title|Xeon W-3223}}
 
{{intel title|Xeon W-3223}}
 
{{chip
 
{{chip
 +
|future=Yes
 
|name=Xeon W-3223
 
|name=Xeon W-3223
−
|image=cascade lake sp (xeon w) (front).png
+
|no image=Yes
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
 
|model number=W-3223
 
|model number=W-3223
 
|part number=CD8069504248402
 
|part number=CD8069504248402
−
|s-spec=SRFFG
 
 
|market=Workstation
 
|market=Workstation
−
|first announced=June 3, 2019
 
−
|first launched=June 3, 2019
 
−
|release price (tray)=$749.00
 
 
|family=Xeon W
 
|family=Xeon W
 
|series=W-3200
 
|series=W-3200
 
|locked=Yes
 
|locked=Yes
 
|frequency=3,500 MHz
 
|frequency=3,500 MHz
−
|turbo frequency1=4,000 MHz
 
−
|bus type=DMI 3.0
 
−
|bus links=4
 
−
|bus rate=8 GT/s
 
 
|clock multiplier=35
 
|clock multiplier=35
 
|isa=x86-64
 
|isa=x86-64
 
|isa family=x86
 
|isa family=x86
 
|microarch=Cascade Lake
 
|microarch=Cascade Lake
−
|core name=Cascade Lake SP
+
|core name=Cascade Lake W
−
|core stepping=B1
 
 
|process=14 nm
 
|process=14 nm
 
|technology=CMOS
 
|technology=CMOS
Line 32: Line 24:
 
|thread count=16
 
|thread count=16
 
|max cpus=1
 
|max cpus=1
−
|max memory=1 TiB
 
 
|tdp=160 W
 
|tdp=160 W
−
|package name 1=intel,fclga_3647
 
 
}}
 
}}
−
'''W-3223''' is a {{arch|64}} [[octa-core]] [[x86]] enterprise performance workstation microprocessor introduced by [[Intel]] in [[2019]]. This processor is fabricated on an enhanced [[14 nm process|14nm++ process]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture. The W-3223 operates at 3.5 GHz with a [[TDP]] of 160 W, a {{intel|turbo boost}} frequency of up to 4 GHz and a {{intel|turbo boost max}} of 4.2 GHz. This chip supports up to 1 TiB of hexa-channel DDR4-2666 memory.
+
'''W-3223''' is a {{arch|64}} [[octa-core]] [[x86]] enterprise performance workstation microprocessor introduced by [[Intel]] in [[2019]]. This processors, which is fabricated on an enhanced [[14 nm process|14nm++ process]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture, operates at 3.5 GHz with a [[TDP]] of 160 W and a {{intel|turbo boost}} frequency of up to ? GHz.
 +
 
 +
 
 +
{{unknown features}}
  
  
−
{{#set:intel turbo boost max technology 3 0 frequency=4.2 GHz}}
 
 
== Cache ==
 
== Cache ==
−
{{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}}
+
{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
−
This processor has a non-default [[level 3 cache]] of 16.5 MiB, an amount usually found in the [[12 cores]] part.
 
 
{{cache size
 
{{cache size
 
|l1 cache=512 KiB
 
|l1 cache=512 KiB
Line 56: Line 47:
 
|l2 desc=16-way set associative
 
|l2 desc=16-way set associative
 
|l2 policy=write-back
 
|l2 policy=write-back
−
|l3 cache=16.5 MiB
+
|l3 cache=11 MiB
−
|l3 break=12x1.375 MiB
+
|l3 break=8x1.375 MiB
 
|l3 desc=11-way set associative
 
|l3 desc=11-way set associative
 
|l3 policy=write-back
 
|l3 policy=write-back
Line 64: Line 55:
 
== Memory controller ==
 
== Memory controller ==
 
{{memory controller
 
{{memory controller
−
|type=DDR4-2666
+
|type=DDR4-2933
 
|ecc=Yes
 
|ecc=Yes
−
|max mem=1 TiB
+
|max mem=768 TiB
 
|controllers=2
 
|controllers=2
 
|channels=6
 
|channels=6
−
|max bandwidth=119.21 GiB/s
+
|max bandwidth=131.13 GiB/s
−
|bandwidth schan=19.87 GiB/s
+
|bandwidth schan=21.86 GiB/s
−
|bandwidth dchan=39.74 GiB/s
+
|bandwidth dchan=43.71 GiB/s
−
|bandwidth qchan=79.47 GiB/s
+
|bandwidth qchan=87.42 GiB/s
−
|bandwidth hchan=119.21 GiB/s
+
|bandwidth hchan=131.13 GiB/s
 
}}
 
}}
  
Line 82: Line 73:
 
|type=PCIe
 
|type=PCIe
 
|pcie revision=3.0
 
|pcie revision=3.0
−
|pcie lanes=64
+
|pcie lanes=48
 
|pcie config=x16
 
|pcie config=x16
 
|pcie config 2=x8
 
|pcie config 2=x8
Line 121: Line 112:
 
|avx512vbmi=No
 
|avx512vbmi=No
 
|avx5124fmaps=No
 
|avx5124fmaps=No
−
|avx512vnni=Yes
 
 
|avx5124vnniw=No
 
|avx5124vnniw=No
 
|avx512vpopcntdq=No
 
|avx512vpopcntdq=No
Line 138: Line 128:
 
|clmul=Yes
 
|clmul=Yes
 
|f16c=Yes
 
|f16c=Yes
−
|bfloat16=No
 
 
|tbt1=No
 
|tbt1=No
 
|tbt2=Yes
 
|tbt2=Yes
−
|tbmt3=Yes
+
|tbmt3=No
−
|tvb=No
 
 
|bpt=No
 
|bpt=No
 
|eist=Yes
 
|eist=Yes
Line 173: Line 161:
 
|osguard=Yes
 
|osguard=Yes
 
|intqat=No
 
|intqat=No
−
|dlboost=Yes
 
 
|3dnow=No
 
|3dnow=No
 
|e3dnow=No
 
|e3dnow=No
Line 187: Line 174:
 
|sensemi=No
 
|sensemi=No
 
|xfr=No
 
|xfr=No
−
|xfr2=No
 
−
|mxfr=No
 
−
|amdpb=No
 
−
|amdpb2=No
 
−
|amdpbod=No
 
−
}}
 
−
 
−
== Documents ==
 
−
* [[:File:w-3200-pb.pdf|Xeon W-3200 Series Product Brief]]
 
−
 
−
== Frequencies ==
 
−
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 
−
{{frequency table
 
−
|freq_base=3,500 MHz
 
−
|freq_1=4,000 MHz
 
−
|freq_2=4,000 MHz
 
−
|freq_3=3,800 MHz
 
−
|freq_4=3,800 MHz
 
−
|freq_5=3,800 MHz
 
−
|freq_6=3,800 MHz
 
−
|freq_7=3,800 MHz
 
−
|freq_8=3,800 MHz
 
−
|freq_avx2_1=3,800 MHz
 
−
|freq_avx2_2=3,800 MHz
 
−
|freq_avx2_3=3,600 MHz
 
−
|freq_avx2_4=3,600 MHz
 
−
|freq_avx2_5=3,500 MHz
 
−
|freq_avx2_6=3,500 MHz
 
−
|freq_avx2_7=3,500 MHz
 
−
|freq_avx2_8=3,500 MHz
 
−
|freq_avx512_1=3,300 MHz
 
−
|freq_avx512_2=3,300 MHz
 
−
|freq_avx512_3=3,100 MHz
 
−
|freq_avx512_4=3,100 MHz
 
−
|freq_avx512_5=3,000 MHz
 
−
|freq_avx512_6=3,000 MHz
 
−
|freq_avx512_7=3,000 MHz
 
−
|freq_avx512_8=3,000 MHz
 
 
}}
 
}}

Please note that all contributions to WikiChip may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see WikiChip:Copyrights for details). Do not submit copyrighted work without permission!

Cancel | Editing help (opens in new window)

Templates used on this page:

Retrieved from "https://en.wikichip.org/wiki/intel/xeon_w/w-3223"
Facts about "Xeon W-3223 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon W-3223 - Intel#pcie +
base frequency3,500 MHz (3.5 GHz, 3,500,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
clock multiplier35 +
core count8 +
core nameCascade Lake SP +
core steppingB1 +
designerIntel +
familyXeon W +
first announcedJune 3, 2019 +
first launchedJune 3, 2019 +
full page nameintel/xeon w/w-3223 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Secure Key Technology +, OS Guard +, Identity Protection Technology +, Turbo Boost Max Technology 3.0 + and Deep Learning Boost +
has intel deep learning boosttrue +
has intel enhanced speedstep technologytrue +
has intel identity protection technology supporttrue +
has intel secure key technologytrue +
has intel speed shift technologytrue +
has intel supervisor mode execution protectiontrue +
has intel trusted execution technologytrue +
has intel turbo boost max technology 3 0true +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
intel turbo boost max technology 3 0 frequency4,200 MHz (4.2 GHz, 4,200,000 kHz) +
isax86-64 +
isa familyx86 +
l1$ size512 KiB (524,288 B, 0.5 MiB) +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description8-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description16-way set associative +
l2$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description11-way set associative +
l3$ size16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) +
ldateJune 3, 2019 +
main imageFile:cascade lake sp (xeon w) (front).png +
manufacturerIntel +
market segmentWorkstation +
max cpu count1 +
max memory1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
max memory bandwidth119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels6 +
microarchitectureCascade Lake +
model numberW-3223 +
nameXeon W-3223 +
number of avx-512 execution units2 +
packageFCLGA-3647 +
part numberCD8069504248402 +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 749.00 (€ 674.10, £ 606.69, ¥ 77,394.17) +
release price (tray)$ 749.00 (€ 674.10, £ 606.69, ¥ 77,394.17) +
s-specSRFFG +
seriesW-3200 +
smp max ways1 +
socketSocket P + and LGA-3647 +
supported memory typeDDR4-2666 +
tdp160 W (160,000 mW, 0.215 hp, 0.16 kW) +
technologyCMOS +
thread count16 +
turbo frequency (1 core)4,000 MHz (4 GHz, 4,000,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensionstrue +