Editing intel/xeon w/w-3223

{{intel title|Xeon W-3223}}
{{chip
|name=Xeon W-3223
|image=cascade lake sp (xeon w) (front).png
|designer=Intel
|manufacturer=Intel
|model number=W-3223
|part number=CD8069504248402
|s-spec=SRFFG
|market=Workstation
|first announced=June 3, 2019
|first launched=June 3, 2019
|release price (tray)=$749.00
|family=Xeon W
|series=W-3200
|locked=Yes
|frequency=3,500 MHz
|turbo frequency1=4,000 MHz
|bus type=DMI 3.0
|bus links=4
|bus rate=8 GT/s
|clock multiplier=35
|isa=x86-64
|isa family=x86
|microarch=Cascade Lake
|core name=Cascade Lake SP
|core stepping=B1
|process=14 nm
|technology=CMOS
|word size=64 bit
|core count=8
|thread count=16
|max cpus=1
|max memory=1 TiB
|tdp=160 W
|package name 1=intel,fclga_3647
}}
'''W-3223''' is a {{arch|64}} [[octa-core]] [[x86]] enterprise performance workstation microprocessor introduced by [[Intel]] in [[2019]]. This processor is fabricated on an enhanced [[14 nm process|14nm++ process]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture. The W-3223 operates at 3.5 GHz with a [[TDP]] of 160 W, a {{intel|turbo boost}} frequency of up to 4 GHz and a {{intel|turbo boost max}} of 4.2 GHz. This chip supports up to 1 TiB of hexa-channel DDR4-2666 memory.


{{#set:intel turbo boost max technology 3 0 frequency=4.2 GHz}}
== Cache ==
{{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}}
This processor has a non-default [[level 3 cache]] of 16.5 MiB, an amount usually found in the [[12 cores]] part.
{{cache size
|l1 cache=512 KiB
|l1i cache=256 KiB
|l1i break=8x32 KiB
|l1i desc=8-way set associative
|l1d cache=256 KiB
|l1d break=8x32 KiB
|l1d desc=8-way set associative
|l1d policy=write-back
|l2 cache=8 MiB
|l2 break=8x1 MiB
|l2 desc=16-way set associative
|l2 policy=write-back
|l3 cache=16.5 MiB
|l3 break=12x1.375 MiB
|l3 desc=11-way set associative
|l3 policy=write-back
}}

== Memory controller ==
{{memory controller
|type=DDR4-2666
|ecc=Yes
|max mem=1 TiB
|controllers=2
|channels=6
|max bandwidth=119.21 GiB/s
|bandwidth schan=19.87 GiB/s
|bandwidth dchan=39.74 GiB/s
|bandwidth qchan=79.47 GiB/s
|bandwidth hchan=119.21 GiB/s
}}

== Expansions ==
{{expansions main
|
{{expansions entry
|type=PCIe
|pcie revision=3.0
|pcie lanes=64
|pcie config=x16
|pcie config 2=x8
|pcie config 3=x4
|pcie config 4=x1
}}
}}

== Features == 
{{x86 features
|real=Yes
|protected=Yes
|smm=Yes
|fpu=Yes
|x8616=Yes
|x8632=Yes
|x8664=Yes
|nx=Yes
|mmx=Yes
|emmx=Yes
|sse=Yes
|sse2=Yes
|sse3=Yes
|ssse3=Yes
|sse41=Yes
|sse42=Yes
|sse4a=No
|avx=Yes
|avx2=Yes
|avx512f=Yes
|avx512cd=Yes
|avx512er=No
|avx512pf=No
|avx512bw=Yes
|avx512dq=Yes
|avx512vl=Yes
|avx512ifma=No
|avx512vbmi=No
|avx5124fmaps=No
|avx512vnni=Yes
|avx5124vnniw=No
|avx512vpopcntdq=No
|avx512units=2
|abm=Yes
|tbm=No
|bmi1=Yes
|bmi2=Yes
|fma3=Yes
|fma4=No
|aes=Yes
|rdrand=Yes
|sha=No
|xop=No
|adx=Yes
|clmul=Yes
|f16c=Yes
|bfloat16=No
|tbt1=No
|tbt2=Yes
|tbmt3=Yes
|tvb=No
|bpt=No
|eist=Yes
|sst=Yes
|flex=No
|fastmem=No
|ivmd=Yes
|intelnodecontroller=No
|intelnode=No
|kpt=No
|ptt=No
|intelrunsure=No
|mbe=No
|isrt=No
|sba=No
|mwt=No
|sipp=No
|att=No
|ipt=Yes
|tsx=Yes
|txt=Yes
|ht=Yes
|vpro=Yes
|vtx=Yes
|vtd=Yes
|ept=Yes
|mpx=Yes
|sgx=No
|securekey=Yes
|osguard=Yes
|intqat=No
|dlboost=Yes
|3dnow=No
|e3dnow=No
|smartmp=No
|powernow=No
|amdvi=No
|amdv=No
|amdsme=No
|amdtsme=No
|amdsev=No
|rvi=No
|smt=No
|sensemi=No
|xfr=No
|xfr2=No
|mxfr=No
|amdpb=No
|amdpb2=No
|amdpbod=No
}}

== Documents ==
* [[:File:w-3200-pb.pdf|Xeon W-3200 Series Product Brief]]

== Frequencies ==
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
{{frequency table
|freq_base=3,500 MHz
|freq_1=4,000 MHz
|freq_2=4,000 MHz
|freq_3=3,800 MHz
|freq_4=3,800 MHz
|freq_5=3,800 MHz
|freq_6=3,800 MHz
|freq_7=3,800 MHz
|freq_8=3,800 MHz
|freq_avx2_1=3,800 MHz
|freq_avx2_2=3,800 MHz
|freq_avx2_3=3,600 MHz
|freq_avx2_4=3,600 MHz
|freq_avx2_5=3,500 MHz
|freq_avx2_6=3,500 MHz
|freq_avx2_7=3,500 MHz
|freq_avx2_8=3,500 MHz
|freq_avx512_1=3,300 MHz
|freq_avx512_2=3,300 MHz
|freq_avx512_3=3,100 MHz
|freq_avx512_4=3,100 MHz
|freq_avx512_5=3,000 MHz
|freq_avx512_6=3,000 MHz
|freq_avx512_7=3,000 MHz
|freq_avx512_8=3,000 MHz
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon W-3223 - Intel#pcie +
base frequency	3,500 MHz (3.5 GHz, 3,500,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
clock multiplier	35 +
core count	8 +
core name	Cascade Lake SP +
core stepping	B1 +
designer	Intel +
family	Xeon W +
first announced	June 3, 2019 +
first launched	June 3, 2019 +
full page name	intel/xeon w/w-3223 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Secure Key Technology +, OS Guard +, Identity Protection Technology +, Turbo Boost Max Technology 3.0 + and Deep Learning Boost +
has intel deep learning boost	true +
has intel enhanced speedstep technology	true +
has intel identity protection technology support	true +
has intel secure key technology	true +
has intel speed shift technology	true +
has intel supervisor mode execution protection	true +
has intel trusted execution technology	true +
has intel turbo boost max technology 3 0	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
intel turbo boost max technology 3 0 frequency	4,200 MHz (4.2 GHz, 4,200,000 kHz) +
isa	x86-64 +
isa family	x86 +
l1$ size	512 KiB (524,288 B, 0.5 MiB) +
l1d$ description	8-way set associative +
l1d$ size	256 KiB (262,144 B, 0.25 MiB) +
l1i$ description	8-way set associative +
l1i$ size	256 KiB (262,144 B, 0.25 MiB) +
l2$ description	16-way set associative +
l2$ size	8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description	11-way set associative +
l3$ size	16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) +
ldate	June 3, 2019 +
main image	+
manufacturer	Intel +
market segment	Workstation +
max cpu count	1 +
max memory	1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
max memory bandwidth	119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels	6 +
microarchitecture	Cascade Lake +
model number	W-3223 +
name	Xeon W-3223 +
number of avx-512 execution units	2 +
package	FCLGA-3647 +
part number	CD8069504248402 +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 749.00 (€ 674.10, £ 606.69, ¥ 77,394.17) +
release price (tray)	$ 749.00 (€ 674.10, £ 606.69, ¥ 77,394.17) +
s-spec	SRFFG +
series	W-3200 +
smp max ways	1 +
socket	Socket P + and LGA-3647 +
supported memory type	DDR4-2666 +
tdp	160 W (160,000 mW, 0.215 hp, 0.16 kW) +
technology	CMOS +
thread count	16 +
turbo frequency (1 core)	4,000 MHz (4 GHz, 4,000,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensions	true +