From WikiChip
Editing intel/xeon silver

Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.

This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.

Latest revision Your text
Line 31: Line 31:
  
 
== Overview ==
 
== Overview ==
−
Released in July 2017, the Xeon Silver are the successor to the {{intel|Xeon E5}}/{{intel|Xeon E7|E7}} families. Xeon Silver is geared toward mid-range workloads dual-socket server. Xeon Silver processors are a set above the {{intel|Xeon Bronze}}, offering additional features such as {{intel|Hyper-Threading}} and {{intel|Turbo Boost}}.
+
Released in July 2017, the Xeon Silver are the successor to the {{intel|Xeon E5}}/{{intel|Xeon E7|E7}} families. Xeon Silver is geared toward mid-range workloads dual-socket server.
  
 
== Members ==
 
== Members ==
−
=== 4100-Series (Skylake) ===
+
=== Skylake ===
−
{{see also|intel/microarchitectures/skylake (server)|l1=Skylake µarch}}
+
{{see also|intel/microarchitectures/skylake|l1=Skylake µarch}}
−
First-generation Xeon Silver processors were introduced in July 2017. Those chips were fabricated on a enhanced [[14 nm process|14nm+ process]] based on the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture which brought a {{intel|Skylake (Server)#Key changes from Broadwell|l=arch|relatively large}} SoC design change from the prior Xeon families. Those processors were the first to move to a {{intel|mesh interconnect}} which introduced a tile-based architecture, bringing the first implementation of {{x86|AVX-512}} along with a rearchitected cache hierarchy designed for server workloads. All of the Silver 4100-series microprocessors feature dual-socket capabilities with up to [[12 cores]] and 24 threads. Additionally, all Xeon Silver processors support:
 
−
 
 
−
* '''Proc:''' [[14 nm process]]
 
−
* '''TDP:''' 70 W, 85 W
 
−
* '''Mem:''' 768 GiB hexa-channel DDR4-2400 ECC memory.
 
−
* '''I/O:''' 48 PCIe Gen 3.0 lanes
 
−
* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, {{x86|AVX-512}}-{{x86|AVX512F|F}}/{{x86|AVX512CD|CD}}/{{x86|AVX512BW|BW}}/{{x86|AVX512DQ|DQ}}/{{x86|AVX512VL|VL}})
 
−
* '''Features:''' {{intel|Hyper-Threading}}, {{intel|Turbo Boost}}, {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT).
 
−
 
 
−
All Xeon Silver processors support QuickAssist Technology which is integrated on the chipset as well as the Omni-Path Architecture on the chipset as well as via discrete PCIe cards. All models also support 2 {{intel|Ultra Path Interconnect}} (UPI) links.
 
−
 
 
−
<!-- NOTE:
 
−
          This table is generated automatically from the data in the actual articles.
 
−
          If a microprocessor is missing from the list, an appropriate article for it needs to be
 
−
          created and tagged accordingly.
 
−
 
 
−
          Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
 
−
-->
 
−
{{comp table start}}
 
−
<table class="comptable sortable tc4 tc5">
 
−
{{comp table header|main|9:List of Skylake-based Xeon Silver Processors}}
 
−
{{comp table header 1|cols=Price, Launched, Cores, Threads, Frequency, Max Turbo, TDP, L2$, L3$}}
 
−
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Silver]] [[microarchitecture::Skylake (server)]]
 
−
|?full page name
 
−
|?model number
 
−
|?release price
 
−
|?first launched
 
−
|?core count
 
−
|?thread count
 
−
|?base frequency#GHz
 
−
|?turbo frequency (1 core)#GHz
 
−
|?tdp
 
−
|?l2$ size
 
−
|?l3$ size
 
−
|format=template
 
−
|template=proc table 3
 
−
|userparam=11
 
−
|mainlabel=-
 
−
}}
 
−
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Silver]] [[microarchitecture::Skylake (server)]]}}
 
−
</table>
 
−
{{comp table end}}
 
−
 
 
−
=== 4200-Series (Cascade Lake) ===
 
−
{{see also|intel/microarchitectures/cascade lake|intel/cores/cascade lake sp|intel/cores/cascade lake r|l1=Cascade Lake µarch|l2=Cascade Lake SP corename|l3=Cascade Lake R corename}}
 
−
Second-generation Xeon Scalable Silver was introduced in early 2019. Those processors are fabricated on an enhanced [[14 nm process]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture which allows for higher clock speeds and introduced a {{intel|Cascade Lake#Key changes from Skylake|l=arch|number of}} hardware changes against the various [[speculative execution]] [[side channel analysis|vulnerabilities]]. Those processors also introduced new {{x86|AVX-512 VNNI|new instructions}} for the [[acceleration]] of machine learning (inference) as well as support for [[persistent memory]]. All 4200-series Xeon Silver processors support:
 
−
 
 
−
* '''Proc:''' [[14 nm process]]
 
−
* '''TDP:''' 70 W, 85 W, 100 W
 
−
* '''Mem:''' 1 TiB hexa-channel DDR4-2400 ECC memory
 
−
* '''I/O:''' 48 PCIe Gen 3.0 lanes
 
−
* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, {{x86|AVX-512}}-{{x86|AVX512F|F}}/{{x86|AVX512CD|CD}}/{{x86|AVX512BW|BW}}/{{x86|AVX512DQ|DQ}}/{{x86|AVX512VL|VL}}/{{x86|AVX512VNNI|VNNI}})
 
−
* '''Features:''' {{intel|Hyper-Threading}}, {{intel|Turbo Boost}}, {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT).
 
−
 
 
−
All Xeon Silver processors support QuickAssist Technology which is integrated on the chipset as well as the Omni-Path Architecture on the chipset as well as via discrete PCIe cards. All models also support 2 {{intel|Ultra Path Interconnect}} (UPI) links.
 
−
 
 
 
<!-- NOTE:  
 
<!-- NOTE:  
 
           This table is generated automatically from the data in the actual articles.
 
           This table is generated automatically from the data in the actual articles.
Line 100: Line 44:
 
-->
 
-->
 
{{comp table start}}
 
{{comp table start}}
−
<table class="comptable sortable tc4 tc5">
+
<table class="comptable sortable tc13 tc14 tc15 tc16 tc17 tc18 tc19 tc20 tc21 tc22">
−
{{comp table header|main|9:List of Cascade Lake-based Xeon Silver Processors}}
+
<tr class="comptable-header"><th>&nbsp;</th><th colspan="20">List of Skylake-based Xeon Silver Processors</th></tr>
−
{{comp table header 1|cols=Price, Launched, Cores, Threads, Frequency, Max Turbo, TDP, L2$, L3$}}
+
<tr class="comptable-header"><th>&nbsp;</th><th colspan="8">Main processor</th></tr>
−
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Silver]] [[microarchitecture::Cascade Lake]]
+
{{comp table header 1|cols=Price, Process, Launched, C, T, Freq, TDP, Max Mem}}
 +
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Silver]] [[microarchitecture::Skylake]]
 
  |?full page name
 
  |?full page name
 
  |?model number
 
  |?model number
 
  |?release price
 
  |?release price
 +
|?process
 
  |?first launched
 
  |?first launched
 
  |?core count
 
  |?core count
 
  |?thread count
 
  |?thread count
 
  |?base frequency#GHz
 
  |?base frequency#GHz
−
|?turbo frequency (1 core)#GHz
 
 
  |?tdp
 
  |?tdp
−
  |?l2$ size
+
  |?max memory#GiB
−
|?l3$ size
 
 
  |format=template
 
  |format=template
 
  |template=proc table 3
 
  |template=proc table 3
−
|valuesep=,
+
  |userparam=10
−
  |userparam=11
 
 
  |mainlabel=-
 
  |mainlabel=-
 
}}
 
}}
−
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Silver]] [[microarchitecture::Cascade Lake]]}}
+
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Silver]] [[microarchitecture::Skylake]]}}
 
</table>
 
</table>
 
{{comp table end}}
 
{{comp table end}}
  
 
== See also ==
 
== See also ==
−
* {{\\|Xeon Bronze}}
+
* {{\\|Xeon Silver}}
 
* {{\\|Xeon Gold}}
 
* {{\\|Xeon Gold}}
 
* {{\\|Xeon Platinum}}
 
* {{\\|Xeon Platinum}}

Please note that all contributions to WikiChip may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see WikiChip:Copyrights for details). Do not submit copyrighted work without permission!

Cancel | Editing help (opens in new window)

Templates used on this page:

Retrieved from "https://en.wikichip.org/wiki/intel/xeon_silver"
Facts about "Xeon Silver - Intel"
RDF feed
designerIntel +
first announcedMay 4, 2017 +
first launchedJuly 11, 2017 +
full page nameintel/xeon silver +
instance ofmicroprocessor family +
instruction set architecturex86-64 +
main designerIntel +
manufacturerIntel +
microarchitectureSkylake +
nameXeon Silver +
packageFCLGA-3647 +
process14 nm (0.014 μm, 1.4e-5 mm) +
socketLGA-3647 +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +