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{{intel title|Xeon Silver 4114T}} | {{intel title|Xeon Silver 4114T}} | ||
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|name=Xeon Silver 4114T | |name=Xeon Silver 4114T | ||
|image=skylake sp (basic).png | |image=skylake sp (basic).png | ||
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|manufacturer=Intel | |manufacturer=Intel | ||
|model number=4114T | |model number=4114T | ||
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|market=Server | |market=Server | ||
|first announced=July 11, 2017 | |first announced=July 11, 2017 | ||
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|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
− | |microarch=Skylake | + | |microarch=Skylake |
|platform=Purley | |platform=Purley | ||
|chipset=Lewisburg | |chipset=Lewisburg | ||
|core name=Skylake SP | |core name=Skylake SP | ||
|core family=6 | |core family=6 | ||
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|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
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|core count=10 | |core count=10 | ||
|thread count=20 | |thread count=20 | ||
+ | |max cpus=2 | ||
|max memory=768 GiB | |max memory=768 GiB | ||
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|tdp=85 W | |tdp=85 W | ||
− | + | |package module 1={{packages/intel/fclga-3647}} | |
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}} | }} | ||
− | '''Xeon Silver 4114T''' is a {{arch|64}} [[deca-core]] [[x86]] dual-socket mid-range performance server microprocessor introduced by [[Intel]] in mid-2017. The Silver 4114T, which is based on the server configuration of the {{intel | + | '''Xeon Silver 4114T''' is a {{arch|64}} [[deca-core]] [[x86]] dual-socket mid-range performance server microprocessor introduced by [[Intel]] in mid-2017. The Silver 4114T, which is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]], sports 1 {{x86|AVX-512}} [[FMA]] unit as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2.2 GHz with a TDP of 85 W and a {{intel|turbo boost}} frequency of up to 3 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory. |
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== Cache == | == Cache == | ||
− | {{main|intel/microarchitectures/ | + | {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} |
{{cache size | {{cache size | ||
|l1 cache=640 KiB | |l1 cache=640 KiB | ||
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| pcie config = x16 | | pcie config = x16 | ||
| pcie config 2 = x8 | | pcie config 2 = x8 | ||
− | | pcie config | + | | pcie config 2 = x4 |
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Facts about "Xeon Silver 4114T - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Silver 4114T - Intel#io + |
base frequency | 2,200 MHz (2.2 GHz, 2,200,000 kHz) + |
chipset | Lewisburg + |
clock multiplier | 22 + |
core count | 10 + |
core family | 6 + |
core name | Skylake SP + |
core stepping | U0 + |
designer | Intel + |
family | Xeon Silver + |
first announced | July 11, 2017 + |
first launched | July 11, 2017 + |
full page name | intel/xeon silver/4114t + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Encryption Standard Instruction Set Extension +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Enhanced SpeedStep Technology +, Extended Page Tables +, Hyper-Threading Technology +, Intel VT-x +, Intel vPro Technology +, Speed Shift Technology +, Transactional Synchronization Extensions +, Trusted Execution Technology + and Turbo Boost Technology 2.0 + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 640 KiB (655,360 B, 0.625 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 320 KiB (327,680 B, 0.313 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 320 KiB (327,680 B, 0.313 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 10 MiB (10,240 KiB, 10,485,760 B, 0.00977 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 13.75 MiB (14,080 KiB, 14,417,920 B, 0.0134 GiB) + |
ldate | July 11, 2017 + |
main image | + |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 350.15 K (77 °C, 170.6 °F, 630.27 °R) + |
max cpu count | 2 + |
max memory | 786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) + |
max memory bandwidth | 107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) + |
max memory channels | 6 + |
max pcie lanes | 48 + |
microarchitecture | Skylake (server) + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
model number | 4114T + |
name | Xeon Silver 4114T + |
package | FCLGA-3647 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
s-spec | SR3MM + |
s-spec (qs) | QN7A + |
series | 4000 + |
smp interconnect | UPI + |
smp interconnect links | 2 + |
smp interconnect rate | 9.6 GT/s + |
smp max ways | 2 + |
socket | LGA-3647 + and Socket P + |
supported memory type | DDR4-2400 + |
tdp | 85 W (85,000 mW, 0.114 hp, 0.085 kW) + |
technology | CMOS + |
thread count | 20 + |
turbo frequency (1 core) | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |