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| isa = x86-64 | | isa = x86-64 | ||
| microarch = Skylake | | microarch = Skylake | ||
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| word = 64 bit | | word = 64 bit | ||
| proc = 14 nm | | proc = 14 nm | ||
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== Members == | == Members == | ||
− | + | === 8100-Series (Skylake) === | |
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{{see also|intel/microarchitectures/skylake (server)|l1=Skylake µarch}} | {{see also|intel/microarchitectures/skylake (server)|l1=Skylake µarch}} | ||
First-generation Xeon Platinum processors were introduced in July 2017. Those chips were fabricated on a enhanced [[14 nm process|14nm+ process]] based on the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture which brought a {{intel|Skylake (Server)#Key changes from Broadwell|l=arch|relatively large}} SoC design change from the prior Xeon families. Those processors were the first to move to a {{intel|mesh interconnect}} which introduced a tile-based architecture, bringing the first implementation of {{x86|AVX-512}} along with a rearchitected cache hierarchy designed for server workloads. All of the platinum 8100-series microprocessors feature eight-way [[SMP]] capabilities with up to [[28 cores]] and 56 threads. Additionally, all Xeon Platinum processors support: | First-generation Xeon Platinum processors were introduced in July 2017. Those chips were fabricated on a enhanced [[14 nm process|14nm+ process]] based on the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture which brought a {{intel|Skylake (Server)#Key changes from Broadwell|l=arch|relatively large}} SoC design change from the prior Xeon families. Those processors were the first to move to a {{intel|mesh interconnect}} which introduced a tile-based architecture, bringing the first implementation of {{x86|AVX-512}} along with a rearchitected cache hierarchy designed for server workloads. All of the platinum 8100-series microprocessors feature eight-way [[SMP]] capabilities with up to [[28 cores]] and 56 threads. Additionally, all Xeon Platinum processors support: | ||
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{{comp table start}} | {{comp table start}} | ||
<table class="comptable sortable tc4 tc5"> | <table class="comptable sortable tc4 tc5"> | ||
− | + | <tr class="comptable-header"><th> </th><th colspan="20">List of Skylake-based Xeon Platinum Processors</th></tr> | |
− | + | <tr class="comptable-header"><th> </th><th colspan="7">Main processor</th><th colspan="2">Cache</th><th colspan="2">Memory</th></tr> | |
{{comp table header 1|cols=Price, Launched, Cores, Threads, %Frequency, %Max Turbo, %TDP, %L2$, %L3$, Mem Type, %Max Mem}} | {{comp table header 1|cols=Price, Launched, Cores, Threads, %Frequency, %Max Turbo, %TDP, %L2$, %L3$, Mem Type, %Max Mem}} | ||
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Platinum]] [[microarchitecture::Skylake (server)]] | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Platinum]] [[microarchitecture::Skylake (server)]] | ||
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}} | }} | ||
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Platinum]] [[microarchitecture::Skylake (server)]]}} | {{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Platinum]] [[microarchitecture::Skylake (server)]]}} | ||
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</table> | </table> | ||
{{comp table end}} | {{comp table end}} |
Facts about "Xeon Platinum - Intel"
designer | Intel + |
first announced | May 4, 2017 + |
first launched | July 11, 2017 + |
full page name | intel/xeon platinum + |
instance of | microprocessor family + |
instruction set architecture | x86-64 + |
main designer | Intel + |
manufacturer | Intel + |
microarchitecture | Skylake +, Cascade Lake + and Cooper Lake + |
name | Xeon Platinum + |
package | FCLGA-3647 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
socket | LGA-3647 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |