From WikiChip
Editing intel/xeon gold/6148
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 1: | Line 1: | ||
{{intel title|Xeon Gold 6148}} | {{intel title|Xeon Gold 6148}} | ||
− | {{ | + | {{mpu |
− | |name=Xeon Gold 6148 | + | | future = Yes |
− | |image= | + | | name = Xeon Gold 6148 |
− | |designer=Intel | + | | no image = Yes |
− | |manufacturer=Intel | + | | image = |
− | |model number=6148 | + | | image size = |
− | |part number= | + | | caption = |
− | |part number 2= | + | | designer = Intel |
− | |s-spec=SR3B6 | + | | manufacturer = Intel |
− | |s-spec | + | | model number = 6148 |
− | |market=Server | + | | part number = CD8067303406200 |
− | |first announced=April 25, 2017 | + | | part number 1 = |
− | |first launched= | + | | part number 2 = |
− | |release price= | + | | s-spec = SR3B6 |
− | |family=Xeon Gold | + | | s-spec 2 = |
− | |series=6100 | + | | market = Server |
− | |locked=Yes | + | | first announced = April 25, 2017 |
− | |frequency=2 | + | | first launched = |
− | |turbo frequency1= | + | | last order = |
− | |bus type=DMI 3.0 | + | | last shipment = |
− | |bus | + | | release price = |
− | |bus rate=8 GT/s | + | |
− | |clock multiplier=24 | + | | family = Xeon Gold |
− | |cpuid= | + | | series = 6100 |
− | |isa=x86-64 | + | | locked = Yes |
− | |isa | + | | frequency = 2.4 GHz |
− | |microarch=Skylake | + | | turbo frequency = |
− | |platform=Purley | + | | turbo frequency1 = |
− | |chipset=Lewisburg | + | | turbo frequency2 = |
− | |core name=Skylake SP | + | | turbo frequency3 = |
− | |core family= | + | | turbo frequency4 = |
− | |core stepping=H0 | + | | turbo frequency5 = |
− | |process=14 nm | + | | turbo frequency6 = |
− | |technology=CMOS | + | | turbo frequency7 = |
− | |word size=64 bit | + | | turbo frequency8 = |
− | |core count=20 | + | | bus type = DMI 3.0 |
− | |thread count=40 | + | | bus speed = |
− | |max memory= | + | | bus rate = 8 GT/s |
− | |max | + | | bus links = 4 |
− | | | + | | clock multiplier = 24 |
− | | | + | | cpuid = |
− | | | + | | cpuid 2 = |
− | | | + | |
− | |tcase min= | + | | isa family = x86-64 |
− | |tcase max= | + | | isa = x86 |
− | | | + | | microarch = Skylake |
− | | | + | | platform = Purley |
− | |package | + | | chipset = Lewisburg |
− | | | + | | core name = Skylake SP |
− | | | + | | core family = |
+ | | core model = | ||
+ | | core stepping = H0 | ||
+ | | process = 14 nm | ||
+ | | transistors = | ||
+ | | technology = CMOS | ||
+ | | die area = <!-- XX mm² --> | ||
+ | | die width = | ||
+ | | die length = | ||
+ | | word size = 64 bit | ||
+ | | core count = 20 | ||
+ | | thread count = 40 | ||
+ | | max cpus = 2 | ||
+ | | max memory = | ||
+ | |||
+ | | electrical = | ||
+ | | power = | ||
+ | | average power = | ||
+ | | idle power = | ||
+ | | v core = | ||
+ | | v core tolerance = <!-- OR ... --> | ||
+ | | v core min = | ||
+ | | v core max = | ||
+ | | v io = | ||
+ | | v io tolerance = | ||
+ | | v io 2 = <!-- OR ... --> | ||
+ | | v io 3 = | ||
+ | | sdp = | ||
+ | | tdp = | ||
+ | | tdp typical = | ||
+ | | ctdp down = | ||
+ | | ctdp down frequency = | ||
+ | | ctdp up = | ||
+ | | ctdp up frequency = | ||
+ | | temp min = <!-- use TJ/TC whenever possible instead --> | ||
+ | | temp max = | ||
+ | | tjunc min = <!-- .. °C --> | ||
+ | | tjunc max = | ||
+ | | tcase min = | ||
+ | | tcase max = | ||
+ | | tstorage min = | ||
+ | | tstorage max = | ||
+ | | tambient min = | ||
+ | | tambient max = | ||
+ | |||
+ | | package module 1 = | ||
+ | | package module 2 = | ||
+ | <!-------- USE ONLY IF MUST, OTHERWISE TRY TO USE MODULE ABOVE --------------> | ||
+ | | packaging = Yes | ||
+ | | package 0 = FCLGA-3647 | ||
+ | | package 0 type = LGA | ||
+ | | package 0 pins = 3647 | ||
+ | | package 0 pitch = | ||
+ | | package 0 width = | ||
+ | | package 0 length = | ||
+ | | package 0 height = | ||
+ | | socket 0 = LGA-3647 | ||
+ | | socket 0 type = LGA | ||
}} | }} | ||
− | '''Xeon Gold 6148''' is a {{arch|64}} [[ | + | '''Xeon Gold 6148''' is a {{arch|64}} [[x86]] high-performance server [[icosa-core]] [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 6148 operates at 2.4 GHz. |
+ | |||
+ | |||
+ | {{unknown features}} | ||
== Cache == | == Cache == | ||
− | {{main|intel/microarchitectures/ | + | {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} |
{{cache size | {{cache size | ||
|l1 cache=1.25 MiB | |l1 cache=1.25 MiB | ||
Line 66: | Line 126: | ||
|l2 cache=20 MiB | |l2 cache=20 MiB | ||
|l2 break=20x1 MiB | |l2 break=20x1 MiB | ||
− | |l2 desc= | + | |l2 desc=4-way set associative |
|l2 policy=write-back | |l2 policy=write-back | ||
|l3 cache=27.5 MiB | |l3 cache=27.5 MiB | ||
|l3 break=20x1.375 MiB | |l3 break=20x1.375 MiB | ||
− | |l3 desc= | + | |l3 desc=16-way set associative |
|l3 policy=write-back | |l3 policy=write-back | ||
}} | }} | ||
Line 78: | Line 138: | ||
|type=DDR4-2666 | |type=DDR4-2666 | ||
|ecc=Yes | |ecc=Yes | ||
− | |max mem= | + | |max mem= |
− | |controllers= | + | |controllers=1 |
|channels=6 | |channels=6 | ||
|max bandwidth=119.21 GiB/s | |max bandwidth=119.21 GiB/s | ||
− | |bandwidth schan=19. | + | |bandwidth schan=19.89 GiB/s |
− | |bandwidth dchan=39. | + | |bandwidth dchan=39.72 GiB/s |
|bandwidth qchan=79.47 GiB/s | |bandwidth qchan=79.47 GiB/s | ||
|bandwidth hchan=119.21 GiB/s | |bandwidth hchan=119.21 GiB/s | ||
}} | }} | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− |
Facts about "Xeon Gold 6148 - Intel"