Editing intel/xeon gold/6138p

{{intel title|Xeon Gold 6138P}}
{{chip
|name=Xeon Gold 6138P
|image=skylake sp p (front).png
|designer=Intel
|manufacturer=Intel
|model number=6138P
|part number=CM8067303824101
|s-spec=SRCUG
|market=Server
|first announced=May 16, 2018
|first launched=May 16, 2018
|release price=$4937
|family=Xeon Gold
|series=6100
|locked=Yes
|frequency=2,000 MHz
|turbo frequency1=3,700 MHz
|bus type=DMI 3.0
|bus links=4
|bus rate=8 GT/s
|clock multiplier=20
|cpuid=0x50654
|isa=x86-64
|isa family=x86
|microarch=Skylake (server)
|platform=Purley
|chipset=Lewisburg
|core name=Skylake SP
|core family=6
|core stepping=H0
|process=14 nm
|technology=CMOS
|mcp=Yes
|die count=2
|word size=64 bit
|core count=20
|thread count=40
|max cpus=2
|max memory=768 GiB
|tdp=195 W
|tcase min=0 °C
|tcase max=86 °C
|dts min=0 °C
|dts max=93 °C
|package name 1=intel,fclga_3647
}}
[[File:skylake-fpga (front, back).jpg|right|thumb|Package]]
'''Xeon Gold 6138P''' is a {{arch|64}} [[20-core]] [[x86]] multi-socket high performance server microprocessor introduced by [[Intel]] in early-[[2018]]. This chip supports up to 2-way multiprocessing. The Gold 6138P, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm+ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 2 GHz with a TDP of 125 W and a {{intel|turbo boost}} frequency of up to 3.7 GHz, supports up 768 GiB of hexa-channel DDR4-2666 ECC memory.

This processor features an Arria 10 GX 1150 [[FPGA]] on-package, offering 1,150,000 [[logic elements]].

== Overview ==
The Xeon Gold 6138P is a special variant of the {{\\|6138}} with almost identical specs except for the TDP, maximum CPU support, and price. For this SKU, Intel is repurposing one of the three {{intel|UPI}} links from the CPU for the FPGA, providing the FPGA with a [[cache coherent]] link to the CPU.

=== FPGA ===
On the same package is an Arria 10 GX 1150 which comes with 1,150,000 [[logic elements]], 427,200 ALM (Intel's adaptive logic modules), and 1,708,800 registers. The FPGA incorporates a number of High-Speed Serial Interface (HSSI) ports which are exposed through the socket and may be used as: 4x 10 GbE KR ports, 2x 40 GbE ports (2x 40 GbE to gearbox or 2x 25 GbE), or 10x 10 GbE CAUI-10 ports.


:[[File:skylake-sp fpga overview.jpg|600px]]

== Cache ==
{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
{{cache size
|l1 cache=1.25 MiB
|l1i cache=640 KiB
|l1i break=20x32 KiB
|l1i desc=8-way set associative
|l1d cache=640 KiB
|l1d break=20x32 KiB
|l1d desc=8-way set associative
|l1d policy=write-back
|l2 cache=20 MiB
|l2 break=20x1 MiB
|l2 desc=16-way set associative
|l2 policy=write-back
|l3 cache=27.5 MiB
|l3 break=20x1.375 MiB
|l3 desc=11-way set associative
|l3 policy=write-back
}}

== Memory controller ==
{{memory controller
|type=DDR4-2666
|ecc=Yes
|max mem=768 GiB
|controllers=2
|channels=6
|max bandwidth=119.21 GiB/s
|bandwidth schan=19.87 GiB/s
|bandwidth dchan=39.74 GiB/s
|bandwidth qchan=79.47 GiB/s
|bandwidth hchan=119.21 GiB/s
}}

== Expansions ==
{{expansions
| pcie revision      = 3.0
| pcie lanes         = 48
| pcie config        = x16
| pcie config 2      = x8
| pcie config 3      = x4
}}

== Features == 
{{x86 features
|real=Yes
|protected=Yes
|smm=Yes
|fpu=Yes
|x8616=Yes
|x8632=Yes
|x8664=Yes
|nx=Yes
|mmx=Yes
|emmx=Yes
|sse=Yes
|sse2=Yes
|sse3=Yes
|ssse3=Yes
|sse41=Yes
|sse42=Yes
|sse4a=No
|avx=Yes
|avx2=Yes
|avx512f=Yes
|avx512cd=Yes
|avx512er=No
|avx512pf=No
|avx512bw=Yes
|avx512dq=Yes
|avx512vl=Yes
|avx512ifma=No
|avx512vbmi=No
|avx5124fmaps=No
|avx5124vnniw=No
|avx512vpopcntdq=No
|abm=Yes
|tbm=No
|bmi1=Yes
|bmi2=Yes
|fma3=Yes
|fma4=No
|aes=Yes
|rdrand=Yes
|sha=No
|xop=No
|adx=Yes
|clmul=Yes
|f16c=Yes
|tbt1=No
|tbt2=Yes
|tbmt3=No
|bpt=No
|eist=Yes
|sst=Yes
|flex=No
|fastmem=No
|ivmd=Yes
|intelnodecontroller=Yes
|intelnode=Yes
|kpt=Yes
|ptt=Yes
|intelrunsure=Yes
|mbe=Yes
|isrt=No
|sba=No
|mwt=No
|sipp=No
|att=No
|ipt=No
|tsx=Yes
|txt=Yes
|ht=Yes
|vpro=Yes
|vtx=Yes
|vtd=Yes
|ept=Yes
|mpx=No
|sgx=No
|securekey=No
|osguard=No
|3dnow=No
|e3dnow=No
|smartmp=No
|powernow=No
|amdvi=No
|amdv=No
|amdsme=No
|amdtsme=No
|amdsev=No
|rvi=No
|smt=No
|sensemi=No
|xfr=No
}}

== Frequencies ==
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
{{frequency table
|freq_base=2,000 MHz
|freq_1=3,700 MHz
|freq_2=3,700 MHz
|freq_3=3,500 MHz
|freq_4=3,500 MHz
|freq_5=3,400 MHz
|freq_6=3,400 MHz
|freq_7=3,400 MHz
|freq_8=3,400 MHz
|freq_9=3,200 MHz
|freq_10=3,200 MHz
|freq_11=3,200 MHz
|freq_12=3,200 MHz
|freq_13=2,900 MHz
|freq_14=2,900 MHz
|freq_15=2,900 MHz
|freq_16=2,900 MHz
|freq_17=2,700 MHz
|freq_18=2,700 MHz
|freq_19=2,700 MHz
|freq_20=2,700 MHz
|freq_avx2_base=1,600 MHz
|freq_avx2_1=3,600 MHz
|freq_avx2_2=3,600 MHz
|freq_avx2_3=3,400 MHz
|freq_avx2_4=3,400 MHz
|freq_avx2_5=3,200 MHz
|freq_avx2_6=3,200 MHz
|freq_avx2_7=3,200 MHz
|freq_avx2_8=3,200 MHz
|freq_avx2_9=2,700 MHz
|freq_avx2_10=2,700 MHz
|freq_avx2_11=2,700 MHz
|freq_avx2_12=2,700 MHz
|freq_avx2_13=2,500 MHz
|freq_avx2_14=2,500 MHz
|freq_avx2_15=2,500 MHz
|freq_avx2_16=2,500 MHz
|freq_avx2_17=2,300 MHz
|freq_avx2_18=2,300 MHz
|freq_avx2_19=2,300 MHz
|freq_avx2_20=2,300 MHz
|freq_avx512_base=1,300 MHz
|freq_avx512_1=3,500 MHz
|freq_avx512_2=3,500 MHz
|freq_avx512_3=3,300 MHz
|freq_avx512_4=3,300 MHz
|freq_avx512_5=2,700 MHz
|freq_avx512_6=2,700 MHz
|freq_avx512_7=2,700 MHz
|freq_avx512_8=2,700 MHz
|freq_avx512_9=2,300 MHz
|freq_avx512_10=2,300 MHz
|freq_avx512_11=2,300 MHz
|freq_avx512_12=2,300 MHz
|freq_avx512_13=2,000 MHz
|freq_avx512_14=2,000 MHz
|freq_avx512_15=2,000 MHz
|freq_avx512_16=2,000 MHz
|freq_avx512_17=1,900 MHz
|freq_avx512_18=1,900 MHz
|freq_avx512_19=1,900 MHz
|freq_avx512_20=1,900 MHz
}}

[[Category:microprocessor models by intel based on skylake extreme core count die]]
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Gold 6138P - Intel#io +
base frequency	2,000 MHz (2 GHz, 2,000,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
chipset	Lewisburg +
clock multiplier	20 +
core count	20 +
core family	6 +
core name	Skylake SP +
core stepping	H0 +
cpuid	0x50654 +
designer	Intel +
die count	2 +
family	Xeon Gold +
first announced	May 16, 2018 +
first launched	May 16, 2018 +
full page name	intel/xeon gold/6138p +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Advanced Vector Extensions 512 +
has intel enhanced speedstep technology	true +
has intel speed shift technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
is multi-chip package	true +
isa	x86-64 +
isa family	x86 +
l1$ size	1,280 KiB (1,310,720 B, 1.25 MiB) +
l1d$ description	8-way set associative +
l1d$ size	640 KiB (655,360 B, 0.625 MiB) +
l1i$ description	8-way set associative +
l1i$ size	640 KiB (655,360 B, 0.625 MiB) +
l2$ description	16-way set associative +
l2$ size	20 MiB (20,480 KiB, 20,971,520 B, 0.0195 GiB) +
l3$ description	11-way set associative +
l3$ size	27.5 MiB (28,160 KiB, 28,835,840 B, 0.0269 GiB) +
ldate	May 16, 2018 +
main image	+
manufacturer	Intel +
market segment	Server +
max case temperature	359.15 K (86 °C, 186.8 °F, 646.47 °R) +
max cpu count	2 +
max dts temperature	93 °C +
max memory	786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) +
max memory bandwidth	119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels	6 +
max pcie lanes	48 +
microarchitecture	Skylake (server) +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min dts temperature	0 °C +
model number	6138P +
name	Xeon Gold 6138P +
package	FCLGA-3647 +
part number	CM8067303824101 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 4,937.00 (€ 4,443.30, £ 3,998.97, ¥ 510,140.21) +
s-spec	SRCUG +
series	6100 +
smp max ways	2 +
socket	Socket P + and LGA-3647 +
supported memory type	DDR4-2666 +
tdp	195 W (195,000 mW, 0.261 hp, 0.195 kW) +
technology	CMOS +
thread count	40 +
turbo frequency (1 core)	3,700 MHz (3.7 GHz, 3,700,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +