Editing intel/xeon gold/5222

{{intel title|Xeon Gold 5222}}
{{chip
|name=Xeon Gold 5222
|image=cascade lake sp (front).png
|designer=Intel
|manufacturer=Intel
|model number=5222
|part number=CD8069504193501
|s-spec=SRF8V
|market=Server
|first announced=April 2, 2019
|first launched=April 2, 2019
|release price (tray)=$1,221.00
|family=Xeon Gold
|series=5200
|locked=Yes
|frequency=3,800 MHz
|turbo frequency1=3,900 MHz
|bus type=DMI 3.0
|bus links=4
|bus rate=8 GT/s
|clock multiplier=38
|cpuid=0x50655
|isa=x86-64
|isa family=x86
|microarch=Cascade Lake
|platform=Purley
|chipset=Lewisburg
|core name=Cascade Lake SP
|core family=6
|core stepping=B1
|process=14 nm
|technology=CMOS
|word size=64 bit
|core count=4
|thread count=8
|max cpus=4
|max memory=1 TiB
|tdp=105 W
|tcase min=0 °C
|tcase max=71 °C
|dts min=0 °C
|dts max=104 °C
|package name 1=intel,fclga_3647
|predecessor=Xeon Gold 5122
|predecessor link=intel/xeon_gold/5122
}}
'''Xeon Gold 5222''' is a {{arch|64}} [[quad-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 5222 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports two {{x86|AVX-512}} [[FMA]] units as well as two {{intel|Ultra Path Interconnect|UPI}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.8 GHz with a TDP of 105 W and features a {{intel|turbo boost}} frequency of up to 3.9 GHz.

Note that this is the only processor in the {{intel|Xeon Gold}} 52xx series with two 512b [[FMA]] units.

== Cache ==
{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
The Xeon Gold 5222 features a considerably larger non-default 16.5 MiB of [[L3]], a size that would normally be found on a 12-core part.
{{cache size
|l1 cache=256 KiB
|l1i cache=128 KiB
|l1i break=4x32 KiB
|l1i desc=8-way set associative
|l1d cache=128 KiB
|l1d break=4x32 KiB
|l1d desc=8-way set associative
|l1d policy=write-back
|l2 cache=4 MiB
|l2 break=4x1 MiB
|l2 desc=16-way set associative
|l2 policy=write-back
|l3 cache=16.5 MiB
|l3 break=12x1.375 MiB
|l3 desc=11-way set associative
|l3 policy=write-back
}}

== Memory controller ==
{{memory controller
|type=DDR4-2933
|ecc=Yes
|max mem=1 TiB
|controllers=2
|channels=6
|max bandwidth=131.13 GiB/s
|bandwidth schan=21.86 GiB/s
|bandwidth dchan=43.71 GiB/s
|bandwidth qchan=87.42 GiB/s
|bandwidth hchan=131.13 GiB/s
}}

== Expansions ==
{{expansions main
|
{{expansions entry
|type=PCIe
|pcie revision=3.0
|pcie lanes=48
|pcie config=1x16
|pcie config 2=x8
|pcie config 3=x4
}}
}}

== Features == 
{{x86 features
|real=Yes
|protected=Yes
|smm=Yes
|fpu=Yes
|x8616=Yes
|x8632=Yes
|x8664=Yes
|nx=Yes
|mmx=Yes
|emmx=Yes
|sse=Yes
|sse2=Yes
|sse3=Yes
|ssse3=Yes
|sse41=Yes
|sse42=Yes
|sse4a=No
|avx=Yes
|avx2=Yes
|avx512f=Yes
|avx512cd=Yes
|avx512er=No
|avx512pf=No
|avx512bw=Yes
|avx512dq=Yes
|avx512vl=Yes
|avx512ifma=No
|avx512vbmi=No
|avx5124fmaps=No
|avx512vnni=Yes
|avx5124vnniw=No
|avx512vpopcntdq=No
|avx512units=2
|abm=Yes
|tbm=No
|bmi1=Yes
|bmi2=Yes
|fma3=Yes
|fma4=No
|aes=Yes
|rdrand=Yes
|sha=No
|xop=No
|adx=Yes
|clmul=Yes
|f16c=Yes
|bfloat16=No
|tbt1=No
|tbt2=Yes
|tbmt3=No
|bpt=No
|eist=Yes
|sst=Yes
|flex=No
|fastmem=No
|ivmd=Yes
|intelnodecontroller=No
|intelnode=Yes
|kpt=Yes
|ptt=Yes
|intelrunsure=No
|mbe=Yes
|isrt=No
|sba=No
|mwt=No
|sipp=No
|att=No
|ipt=No
|tsx=Yes
|txt=Yes
|ht=Yes
|vpro=Yes
|vtx=Yes
|vtd=Yes
|ept=Yes
|mpx=No
|sgx=No
|securekey=No
|osguard=No
|intqat=No
|dlboost=Yes
|3dnow=No
|e3dnow=No
|smartmp=No
|powernow=No
|amdvi=No
|amdv=No
|amdsme=No
|amdtsme=No
|amdsev=No
|rvi=No
|smt=No
|sensemi=No
|xfr=No
|xfr2=No
|mxfr=No
|amdpb=No
|amdpb2=No
|amdpbod=No
}}

== Frequencies ==
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
{{frequency table
|freq_base=3,800MHz 
|freq_1=3,900MHz 
|freq_2=3,900MHz 
|freq_3=3,900MHz 
|freq_4=3,900MHz 
|freq_avx2_base=3,300MHz 
|freq_avx2_1=3,800MHz 
|freq_avx2_2=3,800MHz 
|freq_avx2_3=3,800MHz 
|freq_avx2_4=3,800MHz 
|freq_avx512_base=2,700MHz 
|freq_avx512_1=3,700MHz 
|freq_avx512_2=3,700MHz 
|freq_avx512_3=3,500MHz 
|freq_avx512_4=3,500MHz 
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Gold 5222 - Intel#pcie +
base frequency	3,800 MHz (3.8 GHz, 3,800,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
chipset	Lewisburg +
clock multiplier	38 +
core count	4 +
core family	6 +
core name	Cascade Lake SP +
core stepping	B1 +
cpuid	0x50655 +
designer	Intel +
family	Xeon Gold +
first announced	April 2, 2019 +
first launched	April 2, 2019 +
full page name	intel/xeon gold/5222 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Extended Page Tables +, Transactional Synchronization Extensions +, Intel VT-d + and Deep Learning Boost +
has intel deep learning boost	true +
has intel enhanced speedstep technology	true +
has intel speed shift technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	256 KiB (262,144 B, 0.25 MiB) +
l1d$ description	8-way set associative +
l1d$ size	128 KiB (131,072 B, 0.125 MiB) +
l1i$ description	8-way set associative +
l1i$ size	128 KiB (131,072 B, 0.125 MiB) +
l2$ description	16-way set associative +
l2$ size	4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ description	11-way set associative +
l3$ size	16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) +
ldate	April 2, 2019 +
main image	+
manufacturer	Intel +
market segment	Server +
max case temperature	344.15 K (71 °C, 159.8 °F, 619.47 °R) +
max cpu count	4 +
max dts temperature	104 °C +
max memory	1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
max memory bandwidth	131.13 GiB/s (134,277.12 MiB/s, 140.8 GB/s, 140,799.765 MB/s, 0.128 TiB/s, 0.141 TB/s) +
max memory channels	6 +
microarchitecture	Cascade Lake +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
min dts temperature	0 °C +
model number	5222 +
name	Xeon Gold 5222 +
number of avx-512 execution units	2 +
package	FCLGA-3647 +
part number	CD8069504193501 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 1,221.00 (€ 1,098.90, £ 989.01, ¥ 126,165.93) +
release price (tray)	$ 1,221.00 (€ 1,098.90, £ 989.01, ¥ 126,165.93) +
s-spec	SRF8V +
series	5200 +
smp max ways	4 +
socket	Socket P + and LGA-3647 +
supported memory type	DDR4-2933 +
tdp	105 W (105,000 mW, 0.141 hp, 0.105 kW) +
technology	CMOS +
thread count	8 +
turbo frequency (1 core)	3,900 MHz (3.9 GHz, 3,900,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +