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{{intel title|Xeon Gold 5117}} | {{intel title|Xeon Gold 5117}} | ||
− | {{ | + | {{mpu |
− | |name=Xeon Gold 5117 | + | | future = Yes |
− | |image= | + | | name = Xeon Gold 5117 |
− | |designer=Intel | + | | no image = Yes |
− | |manufacturer=Intel | + | | image = |
− | |model number=5117 | + | | image size = |
− | |s-spec= | + | | caption = |
− | |s-spec | + | | designer = Intel |
− | |market=Server | + | | manufacturer = Intel |
− | |first announced= | + | | model number = 5117 |
− | |first launched= | + | | part number = |
− | |family=Xeon Gold | + | | part number 1 = |
− | |series= | + | | part number 2 = |
− | |locked=Yes | + | | s-spec = |
− | |frequency=2 | + | | s-spec 2 = |
− | |turbo frequency1= | + | | market = Server |
− | |clock multiplier=20 | + | | first announced = April 25, 2017 |
− | |cpuid= | + | | first launched = |
− | |isa=x86 | + | | last order = |
− | |isa | + | | last shipment = |
− | |microarch=Skylake | + | | release price = |
− | |platform=Purley | + | |
− | |chipset=Lewisburg | + | | family = Xeon Gold |
− | |core name=Skylake SP | + | | series = 5000 |
− | |core family= | + | | locked = Yes |
− | |process=14 nm | + | | frequency = 2.0 GHz |
− | |technology=CMOS | + | | turbo frequency = |
− | |word size=64 bit | + | | turbo frequency1 = |
− | |core count= | + | | turbo frequency2 = |
− | |thread count= | + | | turbo frequency3 = |
− | |max cpus= | + | | turbo frequency4 = |
− | |max memory= | + | | turbo frequency5 = |
− | |tdp= | + | | turbo frequency6 = |
− | |tcase min= | + | | turbo frequency7 = |
− | |tcase max= | + | | turbo frequency8 = |
− | |package | + | | bus type = DMI 3.0 |
− | | | + | | bus speed = |
− | | | + | | bus rate = 8 GT/s |
+ | | bus links = 4 | ||
+ | | clock multiplier = 20 | ||
+ | | cpuid = | ||
+ | | cpuid 2 = | ||
+ | |||
+ | | isa family = x86 | ||
+ | | isa = x86-64 | ||
+ | | microarch = Skylake | ||
+ | | platform = Purley | ||
+ | | chipset = Lewisburg | ||
+ | | core name = Skylake SP | ||
+ | | core family = | ||
+ | | core model = | ||
+ | | core stepping = H0 | ||
+ | | process = 14 nm | ||
+ | | transistors = | ||
+ | | technology = CMOS | ||
+ | | die area = <!-- XX mm² --> | ||
+ | | die width = | ||
+ | | die length = | ||
+ | | word size = 64 bit | ||
+ | | core count = 28 | ||
+ | | thread count = 56 | ||
+ | | max cpus = 2 | ||
+ | | max memory = | ||
+ | |||
+ | | electrical = | ||
+ | | power = | ||
+ | | average power = | ||
+ | | idle power = | ||
+ | | v core = | ||
+ | | v core tolerance = <!-- OR ... --> | ||
+ | | v core min = | ||
+ | | v core max = | ||
+ | | v io = | ||
+ | | v io tolerance = | ||
+ | | v io 2 = <!-- OR ... --> | ||
+ | | v io 3 = | ||
+ | | sdp = | ||
+ | | tdp = | ||
+ | | tdp typical = | ||
+ | | ctdp down = | ||
+ | | ctdp down frequency = | ||
+ | | ctdp up = | ||
+ | | ctdp up frequency = | ||
+ | | temp min = <!-- use TJ/TC whenever possible instead --> | ||
+ | | temp max = | ||
+ | | tjunc min = <!-- .. °C --> | ||
+ | | tjunc max = | ||
+ | | tcase min = | ||
+ | | tcase max = | ||
+ | | tstorage min = | ||
+ | | tstorage max = | ||
+ | | tambient min = | ||
+ | | tambient max = | ||
+ | |||
+ | | package module 1 = | ||
+ | | package module 2 = | ||
+ | <!-------- USE ONLY IF MUST, OTHERWISE TRY TO USE MODULE ABOVE --------------> | ||
+ | | packaging = Yes | ||
+ | | package 0 = FCLGA-3647 | ||
+ | | package 0 type = LGA | ||
+ | | package 0 pins = 3647 | ||
+ | | package 0 pitch = | ||
+ | | package 0 width = | ||
+ | | package 0 length = | ||
+ | | package 0 height = | ||
+ | | socket 0 = LGA-3647 | ||
+ | | socket 0 type = LGA | ||
}} | }} | ||
− | '''Xeon Gold 5117''' is a {{arch|64}} [[ | + | '''Xeon Gold 5117''' is a {{arch|64}} [[x86]] high-performance server [[octacosa-core]] [[multiprocessor]] set to be introduced by [[Intel]] in the second quarter of 2017. This processor is based on the server configuration of the {{intel|Skylake|l=arch}} microarchitecture (a {{intel|Skylake SP|l=core}} core) and is manufactured on Intel's [[14 nm process]]. The 5117 operates at 2 GHz. |
+ | |||
+ | |||
+ | {{unknown features}} | ||
== Cache == | == Cache == | ||
− | {{main|intel/microarchitectures/ | + | {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} |
{{cache size | {{cache size | ||
− | |l1 cache= | + | |l1 cache=1.75 MiB |
− | |l1i cache= | + | |l1i cache=896 KiB |
− | |l1i break= | + | |l1i break=28x32 KiB |
|l1i desc=8-way set associative | |l1i desc=8-way set associative | ||
− | |l1d cache= | + | |l1d cache=896 KiB |
− | |l1d break= | + | |l1d break=28x32 KiB |
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
|l1d policy=write-back | |l1d policy=write-back | ||
− | |l2 cache= | + | |l2 cache=28 MiB |
− | |l2 break= | + | |l2 break=28x1 MiB |
|l2 desc=16-way set associative | |l2 desc=16-way set associative | ||
|l2 policy=write-back | |l2 policy=write-back | ||
− | |l3 cache= | + | |l3 cache=38.5 MiB |
− | |l3 break= | + | |l3 break=28x1.375 MiB |
|l3 desc=11-way set associative | |l3 desc=11-way set associative | ||
|l3 policy=write-back | |l3 policy=write-back | ||
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== Memory controller == | == Memory controller == | ||
{{memory controller | {{memory controller | ||
− | |type=DDR4- | + | |type=DDR4-2666 |
|ecc=Yes | |ecc=Yes | ||
− | |max mem= | + | |max mem= |
− | |controllers= | + | |controllers=1 |
|channels=6 | |channels=6 | ||
− | |max bandwidth= | + | |max bandwidth=119.21 GiB/s |
− | |bandwidth schan= | + | |bandwidth schan=19.89 GiB/s |
− | |bandwidth dchan= | + | |bandwidth dchan=39.72 GiB/s |
− | |bandwidth qchan= | + | |bandwidth qchan=79.47 GiB/s |
− | |bandwidth hchan= | + | |bandwidth hchan=119.21 GiB/s |
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}} | }} | ||
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|avx=Yes | |avx=Yes | ||
|avx2=Yes | |avx2=Yes | ||
− | | | + | |avx512=Yes |
− | |||
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− | |||
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− | |||
|abm=Yes | |abm=Yes | ||
|tbm=No | |tbm=No | ||
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|f16c=Yes | |f16c=Yes | ||
|tbt1=No | |tbt1=No | ||
− | |tbt2= | + | |tbt2=No |
|tbmt3=No | |tbmt3=No | ||
|bpt=No | |bpt=No | ||
|eist=Yes | |eist=Yes | ||
− | |sst= | + | |sst=No |
|flex=No | |flex=No | ||
|fastmem=No | |fastmem=No | ||
− | |||
− | |||
− | |||
− | |||
− | |||
|isrt=No | |isrt=No | ||
|sba=No | |sba=No | ||
Line 151: | Line 198: | ||
|ipt=No | |ipt=No | ||
|tsx=Yes | |tsx=Yes | ||
− | |txt= | + | |txt=No |
|ht=Yes | |ht=Yes | ||
|vpro=Yes | |vpro=Yes | ||
|vtx=Yes | |vtx=Yes | ||
− | |vtd= | + | |vtd=Yes |
|ept=Yes | |ept=Yes | ||
− | |mpx= | + | |mpx=Yes |
|sgx=No | |sgx=No | ||
|securekey=No | |securekey=No | ||
− | |osguard= | + | |osguard=Yes |
|3dnow=No | |3dnow=No | ||
|e3dnow=No | |e3dnow=No | ||
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|amdvi=No | |amdvi=No | ||
|amdv=No | |amdv=No | ||
− | |||
− | |||
− | |||
|rvi=No | |rvi=No | ||
|smt=No | |smt=No | ||
Line 175: | Line 219: | ||
|xfr=No | |xfr=No | ||
}} | }} | ||
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Facts about "Xeon Gold 5117 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 5117 - Intel#io + |
base frequency | 2,000 MHz (2 GHz, 2,000,000 kHz) + |
chipset | Lewisburg + |
clock multiplier | 20 + |
core count | 14 + |
core family | 6 + |
core name | Skylake SP + |
cpuid | 0x50654 + |
designer | Intel + |
family | Xeon Gold + |
first announced | July 11, 2017 + |
first launched | July 11, 2017 + |
full page name | intel/xeon gold/5117 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Enhanced SpeedStep Technology +, Intel vPro Technology +, Intel VT-x +, Transactional Synchronization Extensions +, Turbo Boost Technology 2.0 +, Speed Shift Technology +, Trusted Execution Technology +, Extended Page Tables + and Advanced Vector Extensions 512 + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 896 KiB (917,504 B, 0.875 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 448 KiB (458,752 B, 0.438 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 448 KiB (458,752 B, 0.438 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 14 MiB (14,336 KiB, 14,680,064 B, 0.0137 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 19.25 MiB (19,712 KiB, 20,185,088 B, 0.0188 GiB) + |
ldate | July 11, 2017 + |
main image | + |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 354.15 K (81 °C, 177.8 °F, 637.47 °R) + |
max cpu count | 4 + |
max memory | 786,432 MiB (805,306,368 KiB, 824,633,720,832 B, 768 GiB, 0.75 TiB) + |
max memory bandwidth | 107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) + |
max memory channels | 6 + |
max pcie lanes | 48 + |
microarchitecture | Skylake (server) + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
model number | 5117 + |
name | Xeon Gold 5117 + |
package | FCLGA-3647 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
s-spec | SR37S + |
s-spec (qs) | QM8S + |
series | 5100 + |
smp max ways | 4 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2400 + |
tdp | 105 W (105,000 mW, 0.141 hp, 0.105 kW) + |
technology | CMOS + |
thread count | 28 + |
turbo frequency (1 core) | 2,800 MHz (2.8 GHz, 2,800,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |