From WikiChip
Editing intel/xeon e5
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 36: | Line 36: | ||
| predecessor = | | predecessor = | ||
| predecessor link = | | predecessor link = | ||
− | | successor = Xeon | + | | successor = Xeon Bronze |
− | | successor link =intel/xeon | + | | successor link = intel/xeon bronze |
− | | successor 2 = Xeon | + | | successor 2 = Xeon Silver |
− | | successor 2 link = intel/xeon | + | | successor 2 link = intel/xeon silver |
− | | successor 3 = Xeon | + | | successor 3 = Xeon Gold |
− | | successor 3 link = intel/xeon | + | | successor 3 link = intel/xeon gold |
− | | successor 4 = Xeon | + | | successor 4 = Xeon Platinum |
− | | successor 4 | + | | successor 4 link = intel/xeon platinum |
− | |||
− | |||
}} | }} | ||
'''Xeon E5''' is a family of mid-range enterprise-level [[x86]] microprocessors. These server processors offer high performance, multi-socket configuration support, and an extensive set of features. Various models are also used as high-end workstation microprocessors. | '''Xeon E5''' is a family of mid-range enterprise-level [[x86]] microprocessors. These server processors offer high performance, multi-socket configuration support, and an extensive set of features. Various models are also used as high-end workstation microprocessors. | ||
== Members == | == Members == | ||
− | === | + | === Westmere EP === |
{{see also|intel/microarchitectures/westmere|l1=Westmere µarch}} | {{see also|intel/microarchitectures/westmere|l1=Westmere µarch}} | ||
{{empty section}} | {{empty section}} | ||
Line 61: | Line 59: | ||
{{main|intel/microarchitectures/haswell|l1=Haswell µarch}} | {{main|intel/microarchitectures/haswell|l1=Haswell µarch}} | ||
{{empty section}} | {{empty section}} | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
=== Broadwell EP (v4) === | === Broadwell EP (v4) === |
Facts about "Xeon E5 - Intel"
designer | Intel + |
first announced | April 5, 2011 + |
first launched | April 5, 2011 + |
full page name | intel/xeon e5 + |
instance of | microprocessor family + |
instruction set architecture | x86-64 + |
main designer | Intel + |
manufacturer | Intel + |
microarchitecture | Westmere +, Ivy Bridge +, Haswell + and Broadwell + |
name | Intel Xeon E5 + |
package | FCLGA-2011-v3 + |
process | 32 nm (0.032 μm, 3.2e-5 mm) +, 22 nm (0.022 μm, 2.2e-5 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) + |
socket | LGA-2011-v3 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |