From WikiChip
Editing intel/xeon e5/e5-4655 v4

Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.

This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.

Latest revision Your text
Line 1: Line 1:
 
{{intel title|Xeon E5-4655 v4}}
 
{{intel title|Xeon E5-4655 v4}}
−
{{chip
+
{{mpu
−
|name=Xeon E5-4655 v4
+
| name               = Xeon E5-4655 v4
−
|no image=Yes
+
| no image           = Yes
−
|designer=Intel
+
| image              =
−
|manufacturer=Intel
+
| image size          =
−
|model number=E5-4655 v4
+
| caption            =
−
|part number=CM8066002065000
+
| designer           = Intel
−
|s-spec=SR2SH
+
| manufacturer       = Intel
−
|s-spec qs=QKSX
+
| model number       = E5-4655 v4
−
|market=Server
+
| part number         = CM8066002065000
−
|first announced=June 20, 2016
+
| part number 1      =
−
|first launched=June 20, 2016
+
| part number 2      =  
−
|release price=$4616
+
| part number 3      =  
−
|family=Xeon E5
+
| market             = Server
−
|series=E5-4000
+
| first announced     = June 20, 2016
−
|locked=Yes
+
| first launched     = June 20, 2016
−
|frequency=2,500 MHz
+
| last order          =  
−
|turbo frequency1=3,200 MHz
+
| last shipment      =  
−
|turbo frequency2=3,200 MHz
 
−
|turbo frequency3=3,000 MHz
 
−
|turbo frequency4=2,900 MHz
 
−
|turbo frequency5=2,800 MHz
 
−
|turbo frequency6=2,700 MHz
 
−
|turbo frequency7=2,600 MHz
 
−
|turbo frequency8=2,600 MHz
 
−
|turbo frequency=Yes
 
−
|bus type=QPI
 
−
|bus speed=4,800 MHz
 
−
|bus links=2
 
−
|bus rate=9.6 GT/s
 
−
|clock multiplier=25
 
−
|cpuid=406F1
 
−
|isa=x86-64
 
−
|isa family=x86
 
−
|microarch=Broadwell
 
−
|platform=Grantley EP 4S
 
−
|chipset=C610 Series
 
−
|core name=Broadwell EP
 
−
|core family=6
 
−
|core model=4F
 
−
|core stepping=M0
 
−
|process=14 nm
 
−
|transistors=3,200,000,000
 
−
|technology=CMOS
 
−
|word size=64 bit
 
−
|core count=8
 
−
|thread count=16
 
−
|max memory=1,536 GiB
 
−
|max cpus=4
 
−
|v core=1.82 V
 
−
|v io=1.2 V
 
−
|v io tolerance=3%
 
−
|tdp=135 W
 
−
|tcase min=0 °C
 
−
|tcase max=82 °C
 
−
|tstorage min=-25 °C
 
−
|tstorage max=125 °C
 
−
|die size=246.24 mm²
 
−
|packaging=Yes
 
−
|package 0=FCLGA-2011-v3
 
−
|package 0 type=FCLGA
 
−
|package 0 pins=2011
 
−
|package 0 pitch=0.8814 mm
 
−
|package 0 width=52.5 mm
 
−
|package 0 length=45.0 mm
 
−
|package 0 height=5.316 mm
 
−
|socket 0=LGA-2011-v3
 
−
|socket 0 type=LGA
 
−
}}
 
−
The '''Xeon E5-4655 v4''' is a {{arch|64}} [[octa-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for frequency-optimized 4S environments. Operating at 2.5 GHz with a {{intel|turbo boost}} frequency of 3.2 GHz for a single active core, this MPU has a TDP of 135 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
 
  
−
== Cache ==
+
| family              = Xeon E5
−
{{main|intel/microarchitectures/broadwell#Memory_Hierarchy|l1=Broadwell § Cache}}
+
| series              = E5-4000
−
{{cache info
+
| locked              = Yes
−
|l1i cache=256 KiB
+
| frequency          = 2,500 MHz
−
|l1i break=8x32 KiB
+
| turbo frequency    = Yes
−
|l1i desc=8-way set associative
+
| turbo frequency1    = 3,200 MHz
−
|l1i extra=(per core, write-back)
+
| turbo frequency2    =  
−
|l1d cache=256 KiB
+
| bus type            = QPI
−
|l1d break=8x32 KiB
+
| bus speed          = 4,800 MHz
−
|l1d desc=8-way set associative
+
| bus rate            = 9.6 GT/s
−
|l1d extra=(per core, write-back)
+
| bus links          = 2
−
|l2 cache=2 MiB
+
| clock multiplier    = 25
−
|l2 break=8x256 KiB
+
| s-spec              = SR2SH
−
|l2 desc=8-way set associative
+
| s-spec es          =  
−
|l2 extra=(per core, write-back)
+
| s-spec qs          =  
−
|l3 cache=30 MiB
+
| cpuid              = 406F1
−
|l3 break=8x3.75 MiB
 
−
|l3 desc=20-way set associative
 
−
|l3 extra=(shared, per core, write-back)
 
−
}}
 
  
−
== Graphics ==
+
| microarch          = Broadwell
−
This microprocessor has no [[integrated graphics processing unit]].
+
| platform            = Grantley EP 4S
 +
| chipset            = C610 Series
 +
| core name          = Broadwell EP
 +
| core family        = 6
 +
| core model          = 15
 +
| core stepping      = M0
 +
| process            = 14 nm
 +
| transistors        = 3,200,000,000
 +
| technology          = CMOS
 +
| die size            = 246.24 mm²
 +
| word size          = 64 bit
 +
| core count          = 8
 +
| thread count        = 16
 +
| max cpus            = 4
 +
| max memory          = 1,536 GiB
  
−
== Memory controller ==
+
| electrical          = Yes
−
{{integrated memory controller
+
| v core              = 1.82 V
−
| type              = DDR4-2133
+
| v core tolerance    =  
−
| controllers        = 1
+
| v io                = 1.2 V
−
| channels          = 4
+
| v io tolerance      = 3%
−
| ecc support        = Yes
+
| sdp                =  
−
| max bandwidth      = 63.58 GiB/s
+
| tdp                = 135 W
−
| bandwidth schan    = 15.89 GiB/s
+
| ctdp down          =  
−
| bandwidth dchan    = 31.79 GiB/s
+
| ctdp down frequency =  
−
| max memory        = 1,536 GiB
+
| ctdp up            =  
−
| pae                = 46 bit
+
| ctdp up frequency  =  
−
}}
+
| tjunc min          =
−
 
+
| tjunc max          =  
−
== Expansions ==
+
| tcase min          = 0 °C
−
{{expansions
+
| tcase max          = 82 °C
−
| pcie revision      = 3.0
+
| tstorage min       = -25 °C
−
| pcie lanes        = 40
+
| tstorage max        = 125 °C
−
| pcie config       = x4
 
−
| pcie config 1      = x8
 
−
| pcie config 2      = x16
 
−
}}
 
  
−
== Features ==
+
| packaging          = Yes
−
{{x86 features
+
| package 0          = FCLGA-2011-v3
−
| em64t      = Yes
+
| package 0 type     = FCLGA
−
| nx          = Yes
+
| package 0 pins     = 2011
−
| txt        = Yes
+
| package 0 pitch    = 0.8814 mm
−
| tsx        = Yes
+
| package 0 width    = 52.5 mm
−
| vpro        =
+
| package 0 length    = 45.0 mm
−
| ht          = Yes
+
| package 0 height   = 5.316 mm
−
| tbt1        =
+
| socket 0            = LGA-2011-v3
−
| tbt2        = Yes
+
| socket 0 type      = LGA
−
| tbmt3      =
 
−
| bpt        =
 
−
| vt-x        = Yes
 
−
| vt-d        = Yes
 
−
| ept        = Yes
 
−
| mmx        = Yes
 
−
| sse        = Yes
 
−
| sse2        = Yes
 
−
| sse3        = Yes
 
−
| ssse3      = Yes
 
−
| sse4.1     = Yes
 
−
| sse4.2     = Yes
 
−
| aes        = Yes
 
−
| pclmul      = Yes
 
−
| avx        = Yes
 
−
| avx2        = Yes
 
−
| bmi        = Yes
 
−
| bmi1        = Yes
 
−
| bmi2        = Yes
 
−
| f16c        = Yes
 
−
| fma3        = Yes
 
−
| mpx        =
 
−
| sgx        =
 
−
| eist        = Yes
 
−
| secure key  = Yes
 
−
| os guard   = Yes
 
−
| intel at    =  
 
−
| intel ipt  =  
 
 
}}
 
}}
 +
The '''Xeon E5-4655 v4''' is a {{arch|64}} [[hexa-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for frequency-optimized 4S environments. Operating at 2.5 GHz with a {{intel|turbo boost}} frequency of 3.2 GHz for a single active core, this MPU has a TDP of 135 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).

Please note that all contributions to WikiChip may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see WikiChip:Copyrights for details). Do not submit copyrighted work without permission!

Cancel | Editing help (opens in new window)

Templates used on this page:

Retrieved from "https://en.wikichip.org/wiki/intel/xeon_e5/e5-4655_v4"
Facts about "Xeon E5-4655 v4 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon E5-4655 v4 - Intel#io +
base frequency2,500 MHz (2.5 GHz, 2,500,000 kHz) +
bus links2 +
bus rate9,600 MT/s (9.6 GT/s, 9,600,000 kT/s) +
bus speed4,800 MHz (4.8 GHz, 4,800,000 kHz) +
bus typeQPI +
chipsetC610 Series +
clock multiplier25 +
core count8 +
core family6 +
core model4F +
core nameBroadwell EP +
core steppingM0 +
core voltage1.82 V (18.2 dV, 182 cV, 1,820 mV) +
cpuid406F1 +
designerIntel +
die area246.24 mm² (0.382 in², 2.462 cm², 246,240,000 µm²) +
familyXeon E5 +
first announcedJune 20, 2016 +
first launchedJune 20, 2016 +
full page nameintel/xeon e5/e5-4655 v4 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has extended page tables supporttrue +
has featureTrusted Execution Technology +, Transactional Synchronization Extensions +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology + and Extended Page Tables +
has intel enhanced speedstep technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
io voltage1.2 V (12 dV, 120 cV, 1,200 mV) +
io voltage tolerance3% +
isax86-64 +
isa familyx86 +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description8-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description8-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
l3$ description20-way set associative +
l3$ size30 MiB (30,720 KiB, 31,457,280 B, 0.0293 GiB) +
ldateJune 20, 2016 +
manufacturerIntel +
market segmentServer +
max case temperature355.15 K (82 °C, 179.6 °F, 639.27 °R) +
max cpu count4 +
max memory1,572,864 MiB (1,610,612,736 KiB, 1,649,267,441,664 B, 1,536 GiB, 1.5 TiB) +
max pcie lanes40 +
max storage temperature398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitectureBroadwell +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature248.15 K (-25 °C, -13 °F, 446.67 °R) +
model numberE5-4655 v4 +
nameXeon E5-4655 v4 +
part numberCM8066002065000 +
platformGrantley EP 4S +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 4,616.00 (€ 4,154.40, £ 3,738.96, ¥ 476,971.28) +
s-specSR2SH +
s-spec (qs)QKSX +
seriesE5-4000 +
smp max ways4 +
tdp135 W (135,000 mW, 0.181 hp, 0.135 kW) +
technologyCMOS +
thread count16 +
transistor count3,200,000,000 +
turbo frequency (1 core)3,200 MHz (3.2 GHz, 3,200,000 kHz) +
turbo frequency (2 cores)3,200 MHz (3.2 GHz, 3,200,000 kHz) +
turbo frequency (3 cores)3,000 MHz (3 GHz, 3,000,000 kHz) +
turbo frequency (4 cores)2,900 MHz (2.9 GHz, 2,900,000 kHz) +
turbo frequency (5 cores)2,800 MHz (2.8 GHz, 2,800,000 kHz) +
turbo frequency (6 cores)2,700 MHz (2.7 GHz, 2,700,000 kHz) +
turbo frequency (7 cores)2,600 MHz (2.6 GHz, 2,600,000 kHz) +
turbo frequency (8 cores)2,600 MHz (2.6 GHz, 2,600,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +