From WikiChip
Editing intel/xeon e5/e5-1650 v4

Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.

This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.

Latest revision Your text
Line 1: Line 1:
 
{{intel title|Xeon E5-1650 v4}}
 
{{intel title|Xeon E5-1650 v4}}
−
{{chip
+
{{mpu
−
|name=Xeon E5-1650 v4
+
| name               = Xeon E5-1650 v4
−
|no image=Yes
+
| no image           = Yes
−
|designer=Intel
+
| image              =
−
|manufacturer=Intel
+
| image size          =
−
|model number=E5-1650 v4
+
| caption            =
−
|part number=CM8066002044306
+
| designer           = Intel
−
|part number 2=BX80660E51650V4
+
| manufacturer       = Intel
−
|s-spec=SR2P7
+
| model number       = E5-1650 v4
−
|s-spec qs=QKF2
+
| part number         = CM8066002044306
−
|s-spec qs 2=QKVL
+
| part number 1      = BX80660E51650V4
−
|market=Server
+
| part number 2      =  
−
|first announced=June 20, 2016
+
| part number 3      =  
−
|first launched=June 20, 2016
+
| market             = Server
−
|release price=$617.00
+
| first announced     = June 20, 2016
−
|family=Xeon E5
+
| first launched     = June 20, 2016
−
|series=E5-1000
+
| last order          =
−
|locked=Yes
+
| last shipment      =
−
|frequency=3,600 MHz
+
| release price       = $617.00
−
|turbo frequency1=4,000 MHz
+
 
−
|turbo frequency2=4,000 MHz
+
| family             = Xeon E5
−
|turbo frequency3=3,800 MHz
+
| series             = E5-1000
−
|turbo frequency4=3,800 MHz
+
| locked             = Yes
−
|turbo frequency5=3,800 MHz
+
| frequency           = 3,600 MHz
−
|turbo frequency6=3,800 MHz
+
| turbo frequency    = Yes
−
|turbo frequency=Yes
+
| turbo frequency1    = 4,000 MHz
−
|bus type=DMI 2.0
+
| turbo frequency2    =  
−
|bus rate=5 GT/s
+
| bus type           = DMI 2.0
−
|clock multiplier=36
+
| bus speed          =
−
|cpuid=406F1
+
| bus rate           = 5 GT/s
−
|microarch=Broadwell
+
| bus links          =
−
|platform=Grantley EP Workstation
+
| clock multiplier   = 36
−
|chipset=C610 Series
+
| s-spec              = SR2P7
−
|core name=Broadwell EP
+
| s-spec es          =
−
|core family=6
+
| s-spec qs          =
−
|core model=4F
+
| cpuid               = 406F1
−
|core stepping=R0
+
 
−
|process=14 nm
+
| microarch           = Broadwell
−
|transistors=3,200,000,000
+
| platform           = Grantley EP Workstation
−
|technology=CMOS
+
| chipset             = C610 Series
−
|word size=64 bit
+
| core name           = Broadwell EP
−
|core count=6
+
| core family         = 6
−
|thread count=12
+
| core model         = 4F
−
|max memory=1,536 GiB
+
| core stepping       = R0
−
|max cpus=1
+
| process             = 14 nm
−
|v core=1.82 V
+
| transistors         = 3,200,000,000
−
|v io=1.2 V
+
| technology         = CMOS
−
|v io tolerance=3%
+
| die size            = 246.24 mm²
−
|tdp=140 W
+
| word size           = 64 bit
−
|tcase min=0 °C
+
| core count         = 6
−
|tcase max=69 °C
+
| thread count       = 12
−
|tstorage min=-25 °C
+
| max cpus            = 1
−
|tstorage max=125 °C
+
| max memory         = 1,536 GiB
−
|die size=246.24 mm²
+
 
−
|packaging=Yes
+
| electrical          = Yes
−
|package 0=FCLGA-2011-v3
+
| v core             = 1.82 V
−
|package 0 type=FCLGA
+
| v core tolerance    =
−
|package 0 pins=2011
+
| v io               = 1.2 V
−
|package 0 pitch=0.8814 mm
+
| v io tolerance     = 3%
−
|package 0 width=52.5 mm
+
| sdp                =
−
|package 0 length=45.0 mm
+
| tdp                 = 140 W
−
|package 0 height=5.316 mm
+
| ctdp down          =
−
|socket 0=LGA-2011-v3
+
| ctdp down frequency =
−
|socket 0 type=LGA
+
| ctdp up            =
 +
| ctdp up frequency  =
 +
| tjunc min          =
 +
| tjunc max          =
 +
| tcase min           = 0 °C
 +
| tcase max           = 69 °C
 +
| tstorage min       = -25 °C
 +
| tstorage max       = 125 °C
 +
 
 +
| packaging           = Yes
 +
| package 0           = FCLGA-2011-v3
 +
| package 0 type     = FCLGA
 +
| package 0 pins     = 2011
 +
| package 0 pitch     = 0.8814 mm
 +
| package 0 width     = 52.5 mm
 +
| package 0 length   = 45.0 mm
 +
| package 0 height   = 5.316 mm
 +
| socket 0           = LGA-2011-v3
 +
| socket 0 type       = LGA
 
}}
 
}}
 
The '''Xeon E5-1650 v4''' is a {{arch|64}} [[hexa-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for 1S workstations. Operating at 3.6 GHz with a {{intel|turbo boost}} frequency of 4 GHz for a single active core, this MPU has a TDP of 140 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
 
The '''Xeon E5-1650 v4''' is a {{arch|64}} [[hexa-core]] [[x86]] microprocessor introduced by [[Intel]] in 2016. This server MPU is designed for 1S workstations. Operating at 3.6 GHz with a {{intel|turbo boost}} frequency of 4 GHz for a single active core, this MPU has a TDP of 140 W and is manufactured on a [[14 nm process]] (based on {{intel|Broadwell|l=arch}}).
Line 105: Line 123:
  
 
== Expansions ==
 
== Expansions ==
−
{{expansions
+
{{mpu expansions
 
| pcie revision      = 3.0
 
| pcie revision      = 3.0
 
| pcie lanes        = 40
 
| pcie lanes        = 40
Line 114: Line 132:
  
 
== Features ==  
 
== Features ==  
−
{{x86 features
+
{{mpu features
−
|real=No
+
| em64t      = Yes
−
|protected=No
+
| nx         = Yes
−
|smm=No
+
| txt        = Yes
−
|fpu=No
+
| tsx        = Yes
−
|x8616=No
+
| vpro        = Yes
−
|x8632=No
+
| ht          = Yes
−
|x8664=No
+
| tbt1        =  
−
|nx=Yes
+
| tbt2        = Yes
−
|mmx=Yes
+
| tbmt3      = Yes
−
|emmx=No
+
| bpt        =  
−
|sse=Yes
+
| vt-x        = Yes
−
|sse2=Yes
+
| vt-d        = Yes
−
|sse3=Yes
+
| ept        = Yes
−
|ssse3=Yes
+
| mmx        = Yes
−
|sse41=No
+
| sse        = Yes
−
|sse42=No
+
| sse2        = Yes
−
|sse4a=No
+
| sse3        = Yes
−
|avx=Yes
+
| ssse3      = Yes
−
|avx2=Yes
+
| sse4.1      = Yes
−
|avx512f=No
+
| sse4.2      = Yes
−
|avx512cd=No
+
| aes        = Yes
−
|avx512er=No
+
| pclmul      = Yes
−
|avx512pf=No
+
| avx        = Yes
−
|avx512bw=No
+
| avx2        = Yes
−
|avx512dq=No
+
| bmi        = Yes
−
|avx512vl=No
+
| bmi1        = Yes
−
|avx512ifma=No
+
| bmi2        = Yes
−
|avx512vbmi=No
+
| f16c        = Yes
−
|avx5124fmaps=No
+
| fma3        = Yes
−
|avx5124vnniw=No
+
| mpx        =  
−
|avx512vpopcntdq=No
+
| sgx        =  
−
|abm=No
+
| eist        = Yes
−
|tbm=No
+
| secure key = Yes
−
|bmi1=Yes
+
| os guard   = Yes
−
|bmi2=Yes
+
| intel at    =
−
|fma3=Yes
+
| intel ipt   = Yes
−
|fma4=No
 
−
|aes=Yes
 
−
|rdrand=No
 
−
|sha=No
 
−
|xop=No
 
−
|adx=No
 
−
|clmul=No
 
−
|f16c=Yes
 
−
|tbt1=No
 
−
|tbt2=Yes
 
−
|tbmt3=No
 
−
|bpt=No
 
−
|eist=Yes
 
−
|sst=No
 
−
|flex=No
 
−
|fastmem=No
 
−
|ivmd=No
 
−
|intelnodecontroller=No
 
−
|intelnode=No
 
−
|kpt=No
 
−
|ptt=No
 
−
|intelrunsure=No
 
−
|mbe=No
 
−
|isrt=No
 
−
|sba=No
 
−
|mwt=No
 
−
|sipp=No
 
−
|att=No
 
−
|ipt=No
 
−
|tsx=Yes
 
−
|txt=Yes
 
−
|ht=Yes
 
−
|vpro=Yes
 
−
|vtx=No
 
−
|vtd=No
 
−
|ept=Yes
 
−
|mpx=No
 
−
|sgx=No
 
−
|securekey=No
 
−
|osguard=No
 
−
|intqat=No
 
−
|3dnow=No
 
−
|e3dnow=No
 
−
|smartmp=No
 
−
|powernow=No
 
−
|amdvi=No
 
−
|amdv=No
 
−
|amdsme=No
 
−
|amdtsme=No
 
−
|amdsev=No
 
−
|rvi=No
 
−
|smt=No
 
−
|sensemi=No
 
−
|xfr=No
 
−
|mxfr=No
 
−
|amdpb=No
 
−
|amdpb2=No
 
−
|em64t=Yes
 
−
|vt-x=Yes
 
−
|vt-d=Yes
 
−
|sse4_1=Yes
 
−
|sse4_2=Yes
 
−
|pclmul=Yes
 
−
|bmi=Yes
 
−
|secure key=Yes
 
−
|os guard=Yes
 
−
|intel ipt=Yes
 
 
}}
 
}}

Please note that all contributions to WikiChip may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see WikiChip:Copyrights for details). Do not submit copyrighted work without permission!

Cancel | Editing help (opens in new window)

Templates used on this page:

Retrieved from "https://en.wikichip.org/wiki/intel/xeon_e5/e5-1650_v4"
Facts about "Xeon E5-1650 v4 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon E5-1650 v4 - Intel#io +
base frequency3,600 MHz (3.6 GHz, 3,600,000 kHz) +
bus rate5,000 MT/s (5 GT/s, 5,000,000 kT/s) +
bus typeDMI 2.0 +
chipsetC610 Series +
clock multiplier36 +
core count6 +
core family6 +
core model4F +
core nameBroadwell EP +
core steppingR0 +
core voltage1.82 V (18.2 dV, 182 cV, 1,820 mV) +
cpuid406F1 +
designerIntel +
die area246.24 mm² (0.382 in², 2.462 cm², 246,240,000 µm²) +
familyXeon E5 +
first announcedJune 20, 2016 +
first launchedJune 20, 2016 +
full page nameintel/xeon e5/e5-1650 v4 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has extended page tables supporttrue +
has featureAdvanced Encryption Standard Instruction Set Extension +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Enhanced SpeedStep Technology +, Extended Page Tables +, Hyper-Threading Technology +, Intel vPro Technology +, Transactional Synchronization Extensions +, Trusted Execution Technology + and Turbo Boost Technology 2.0 +
has intel enhanced speedstep technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
io voltage1.2 V (12 dV, 120 cV, 1,200 mV) +
io voltage tolerance3% +
l1d$ description8-way set associative +
l1d$ size192 KiB (196,608 B, 0.188 MiB) +
l1i$ description8-way set associative +
l1i$ size192 KiB (196,608 B, 0.188 MiB) +
l2$ description8-way set associative +
l2$ size1.5 MiB (1,536 KiB, 1,572,864 B, 0.00146 GiB) +
l3$ description20-way set associative +
l3$ size15 MiB (15,360 KiB, 15,728,640 B, 0.0146 GiB) +
ldateJune 20, 2016 +
manufacturerIntel +
market segmentServer +
max case temperature342.15 K (69 °C, 156.2 °F, 615.87 °R) +
max cpu count1 +
max memory1,572,864 MiB (1,610,612,736 KiB, 1,649,267,441,664 B, 1,536 GiB, 1.5 TiB) +
max pcie lanes40 +
max storage temperature398.15 K (125 °C, 257 °F, 716.67 °R) +
microarchitectureBroadwell +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
min storage temperature248.15 K (-25 °C, -13 °F, 446.67 °R) +
model numberE5-1650 v4 +
nameXeon E5-1650 v4 +
part numberBX80660E51650V4 + and CM8066002044306 +
platformGrantley EP Workstation +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 617.00 (€ 555.30, £ 499.77, ¥ 63,754.61) +
s-specSR2P7 +
s-spec (qs)QKF2 + and QKVL +
seriesE5-1000 +
smp max ways1 +
tdp140 W (140,000 mW, 0.188 hp, 0.14 kW) +
technologyCMOS +
thread count12 +
transistor count3,200,000,000 +
turbo frequency (1 core)4,000 MHz (4 GHz, 4,000,000 kHz) +
turbo frequency (2 cores)4,000 MHz (4 GHz, 4,000,000 kHz) +
turbo frequency (3 cores)3,800 MHz (3.8 GHz, 3,800,000 kHz) +
turbo frequency (4 cores)3,800 MHz (3.8 GHz, 3,800,000 kHz) +
turbo frequency (5 cores)3,800 MHz (3.8 GHz, 3,800,000 kHz) +
turbo frequency (6 cores)3,800 MHz (3.8 GHz, 3,800,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +