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{{intel title|Xeon E3-1505L v5}} | {{intel title|Xeon E3-1505L v5}} | ||
− | {{ | + | {{mpu |
|name=Xeon E3-1505L v5 | |name=Xeon E3-1505L v5 | ||
|no image=Yes | |no image=Yes | ||
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|part number=CL8066202399804 | |part number=CL8066202399804 | ||
|s-spec=SR2E0 | |s-spec=SR2E0 | ||
− | |market= | + | |market=Mobile |
− | |first announced=September | + | |first announced=September, 2015 |
− | |first launched=October | + | |first launched=October, 2015 |
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|family=Xeon E3 | |family=Xeon E3 | ||
|series=E3-1500 v5 | |series=E3-1500 v5 | ||
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|microarch=Skylake | |microarch=Skylake | ||
|platform=Greenlow | |platform=Greenlow | ||
+ | |chipset=Silver Pass | ||
|core name=Skylake H | |core name=Skylake H | ||
|core family=6 | |core family=6 | ||
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|max cpus=1 | |max cpus=1 | ||
|max memory=64 GiB | |max memory=64 GiB | ||
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|tdp=25 W | |tdp=25 W | ||
|temp min=0 °C | |temp min=0 °C | ||
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|tstorage max=125 °C | |tstorage max=125 °C | ||
|package module 1={{packages/intel/fcbga-1440}} | |package module 1={{packages/intel/fcbga-1440}} | ||
+ | |turbo frequency=Yes | ||
+ | |packaging=Yes | ||
+ | |package=FCBGA1440 | ||
+ | |package type=FCBGA | ||
+ | |package size=42mm x 28mm | ||
+ | |socket=BGA1440 | ||
+ | |socket type=BGA | ||
}} | }} | ||
− | '''Xeon E3-1505L | + | The '''Xeon E3-1505L V5''' is {{arch|64}} [[x86]] quad-core microprocessor for introduced by [[Intel]] in October 2015. This entry-level {{intel|Skylake}}-based embedded processor operates at 2 GHz with turbo boost of 2.8 GHz. This chip has a TDP of 25 Watts. The MPU supports up to 64 GiB of dual-channel DDR3/4 and has the {{intel|HD Graphics P530}} [[integrated graphics processor|IGP]]. |
== Cache == | == Cache == | ||
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} | {{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}} | ||
− | {{cache | + | {{cache info |
− | |||
|l1i cache=128 KiB | |l1i cache=128 KiB | ||
|l1i break=4x32 KiB | |l1i break=4x32 KiB | ||
|l1i desc=8-way set associative | |l1i desc=8-way set associative | ||
+ | |l1i extra=(per core, write-back) | ||
|l1d cache=128 KiB | |l1d cache=128 KiB | ||
|l1d break=4x32 KiB | |l1d break=4x32 KiB | ||
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
− | |l1d | + | |l1d extra=(per core, write-back) |
|l2 cache=1 MiB | |l2 cache=1 MiB | ||
|l2 break=4x256 KiB | |l2 break=4x256 KiB | ||
|l2 desc=4-way set associative | |l2 desc=4-way set associative | ||
− | |l2 | + | |l2 extra=(per core) |
|l3 cache=8 MiB | |l3 cache=8 MiB | ||
|l3 break=4x2 MiB | |l3 break=4x2 MiB | ||
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}} | }} | ||
== Graphics == | == Graphics == | ||
− | {{integrated | + | {{integrated graphic |
− | | gpu = HD Graphics P530 | + | | gpu = Intel HD Graphics P530 |
| device id = 0x191D | | device id = 0x191D | ||
− | |||
| execution units = 24 | | execution units = 24 | ||
− | | | + | | displays = 3 |
+ | | frequency = 350 MHz | ||
+ | | max frequency = 1 GHz | ||
| max memory = 1.7 GiB | | max memory = 1.7 GiB | ||
− | |||
− | |||
| output crt = | | output crt = | ||
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| output dvi = Yes | | output dvi = Yes | ||
− | | directx ver | + | | directx ver = 12.1 |
− | | opengl ver | + | | opengl ver = 4.4 |
− | | opencl ver | + | | opencl ver = 2.0 |
− | | | + | | opengl es ver = |
− | | | + | | hdmi ver = 1.4 |
− | | | + | | dvi ver = |
− | | | + | | dsi ver = |
− | | | + | | vulkan ver = |
− | | | + | | dp ver = 1.2 |
− | | | + | | edp ver = 1.3 |
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− | | | + | | max res hdmi = 4096x2160 |
− | | intel quick sync | + | | max res hdmi freq = 24 Hz |
− | | intel intru 3d | + | | max res dvi = |
− | | intel insider | + | | max res dvi freq = |
− | | intel widi | + | | max res dsi = |
− | | intel fdi | + | | max res dsi freq = |
− | | intel clear video | + | | max res dp = 4096x2304 |
− | | | + | | max res dp freq = 60 Hz |
+ | | max res edp = 4096x2304 | ||
+ | | max res edp freq = 60 Hz | ||
+ | | max res vga = | ||
+ | | max res vga freq = | ||
+ | |||
+ | | intel quick sync = Yes | ||
+ | | intel intru 3d = Yes | ||
+ | | intel insider = Yes | ||
+ | | intel widi = Yes | ||
+ | | intel fdi = | ||
+ | | intel clear video = Yes | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{integrated memory controller | ||
+ | | type = LPDDR3-1600 | ||
+ | | type 2 = LPDDR3-1866 | ||
+ | | type 3 = DDR4-1866 | ||
+ | | type 4 = DDR4-2133 | ||
+ | | controllers = 1 | ||
+ | | channels = 2 | ||
+ | | ecc support = Yes | ||
+ | | max bandwidth = 34.1 GB/s | ||
+ | | bandwidth schan = | ||
+ | | bandwidth dchan = | ||
+ | | max memory = 64 GiB | ||
}} | }} | ||
− | |||
− | == | + | == Expansions == |
− | {{ | + | {{mpu expansions |
− | | | + | | pcie revision = 3.0 |
− | | | + | | pcie lanes = 16 |
− | | | + | | pcie config = 1x16 |
− | | | + | | pcie config 1 = 2x8 |
− | | | + | | pcie config 2 = 1x8+2x4 |
− | | | + | | usb revision = |
− | | | + | | usb revision 2 = |
− | | | + | | usb revision N = |
− | | | + | | usb ports = |
− | | | + | | sata ports = |
− | | | + | | integrated lan = |
− | | | + | | uart = |
− | + | }} | |
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− | + | == Features == | |
− | + | {{mpu features | |
− | + | | em64t = Yes | |
− | + | | nx = Yes | |
− | | | + | | txt = Yes |
− | | | + | | tsx = Yes |
− | + | | vpro = Yes | |
− | | | + | | ht = Yes |
− | | | + | | tbt1 = |
− | + | | tbt2 = Yes | |
− | + | | bpt = | |
− | | | + | | vt-x = Yes |
− | | | + | | vt-d = Yes |
− | |tbt1= | + | | ept = Yes |
− | |tbt2=Yes | + | | mmx = Yes |
− | + | | sse = Yes | |
− | |bpt= | + | | sse2 = Yes |
− | | | + | | sse3 = Yes |
− | | | + | | ssse3 = Yes |
− | | | + | | sse4 = Yes |
− | | | + | | sse4.1 = Yes |
− | | | + | | sse4.2 = Yes |
− | | | + | | aes = Yes |
− | | | + | | pclmul = Yes |
− | | | + | | avx = Yes |
− | | | + | | avx2 = Yes |
− | | | + | | bmi = Yes |
− | | | + | | bmi1 = Yes |
− | | | + | | bmi2 = Yes |
− | | | + | | f16c = Yes |
− | | | + | | fma3 = Yes |
− | | | + | | mpx = Yes |
− | | | + | | sgx = Yes |
− | | | + | | eist = Yes |
− | | | + | | secure key = Yes |
− | | | + | | os guard = Yes |
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}} | }} |
Facts about "Xeon E3-1505L v5 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon E3-1505L v5 - Intel#package + and Xeon E3-1505L v5 - Intel#io + |
base frequency | 2,000 MHz (2 GHz, 2,000,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
clock multiplier | 20 + |
core count | 4 + |
core family | 6 + |
core model | 94 + |
core name | Skylake H + |
core stepping | R0 + |
core voltage (max) | 1.52 V (15.2 dV, 152 cV, 1,520 mV) + |
core voltage (min) | 0.55 V (5.5 dV, 55 cV, 550 mV) + |
designer | Intel + |
device id | 0x191D + |
die area | 122 mm² (0.189 in², 1.22 cm², 122,000,000 µm²) + |
family | Xeon E3 + |
first announced | September 1, 2015 + |
first launched | October 12, 2015 + |
full page name | intel/xeon e3/e3-1505l v5 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Intel VT-x +, Intel VT-d +, OS Guard +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Trusted Execution Technology +, Intel vPro Technology +, Transactional Synchronization Extensions +, Secure Key Technology +, Extended Page Tables +, Memory Protection Extensions + and Software Guard Extensions + |
has intel enhanced speedstep technology | true + |
has intel secure key technology | true + |
has intel supervisor mode execution protection | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
integrated gpu | HD Graphics P530 + |
integrated gpu base frequency | 350 MHz (0.35 GHz, 350,000 KHz) + |
integrated gpu designer | Intel + |
integrated gpu execution units | 24 + |
integrated gpu max frequency | 1,000 MHz (1 GHz, 1,000,000 KHz) + |
integrated gpu max memory | 1,740.8 MiB (1,782,579.2 KiB, 1,825,361,100.8 B, 1.7 GiB) + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 4-way set associative + |
l2$ size | 1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + |
l3$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
ldate | October 12, 2015 + |
main image | + |
manufacturer | Intel + |
market segment | Embedded + |
max cpu count | 1 + |
max junction temperature | 373.15 K (100 °C, 212 °F, 671.67 °R) + |
max memory | 65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) + |
max memory bandwidth | 31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
max memory channels | 2 + |
max operating temperature | 100 °C + |
max pcie lanes | 16 + |
max storage temperature | 398.15 K (125 °C, 257 °F, 716.67 °R) + |
microarchitecture | Skylake + |
min junction temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
min operating temperature | 0 °C + |
min storage temperature | 248.15 K (-25 °C, -13 °F, 446.67 °R) + |
model number | E3-1505L v5 + |
name | Xeon E3-1505L v5 + |
package | FCBGA-1440 + |
part number | CL8066202399804 + |
platform | Greenlow + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 433.00 (€ 389.70, £ 350.73, ¥ 44,741.89) + |
s-spec | SR2E0 + |
series | E3-1500 v5 + |
smp max ways | 1 + |
supported memory type | LPDDR3-1866 +, DDR3L-1600 + and DDR4-2133 + |
tdp | 25 W (25,000 mW, 0.0335 hp, 0.025 kW) + |
technology | CMOS + |
thread count | 8 + |
turbo frequency (1 core) | 2,800 MHz (2.8 GHz, 2,800,000 kHz) + |
turbo frequency (2 cores) | 2,700 MHz (2.7 GHz, 2,700,000 kHz) + |
turbo frequency (3 cores) | 2,600 MHz (2.6 GHz, 2,600,000 kHz) + |
turbo frequency (4 cores) | 2,550 MHz (2.55 GHz, 2,550,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |
x86/has memory protection extensions | true + |
x86/has software guard extensions | true + |