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* '''Proc:''' [[14 nm process]] | * '''Proc:''' [[14 nm process]] | ||
− | * '''Mem:''' Up to 128 [[GiB]] of | + | * '''Mem:''' Up to 128 [[GiB]] of 2666 MT/s [[DDR4]] |
* '''I/O:''' x16 PCIe Gen 3.0 lanes | * '''I/O:''' x16 PCIe Gen 3.0 lanes | ||
* '''TDP:''' 65-95 W | * '''TDP:''' 65-95 W | ||
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{{intel|Coffee Lake|l=arch}}-based Xeon Es were introduced in early 2018. All models have the following features in common: | {{intel|Coffee Lake|l=arch}}-based Xeon Es were introduced in early 2018. All models have the following features in common: | ||
− | * ''' | + | * '''CPU:''' [[hexa-core]] with {{intel|Hyper-Threading}}, 12 MiB L3 |
− | * '''Mem:''' Up to | + | * '''Mem:''' Up to 64 [[GiB]] of 2666 MT/s [[DDR4]] |
* '''I/O:''' PCIe Gen 3.0 x16 lanes | * '''I/O:''' PCIe Gen 3.0 x16 lanes | ||
* '''TDP:''' 45 W | * '''TDP:''' 45 W | ||
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* '''Proc:''' [[14 nm process]] | * '''Proc:''' [[14 nm process]] | ||
− | * '''Mem:''' Up to 128 [[GiB]] of | + | * '''Mem:''' Up to 128 [[GiB]] of 2666 MT/s [[DDR4]] |
* '''I/O:''' x16 PCIe Gen 3.0 lanes | * '''I/O:''' x16 PCIe Gen 3.0 lanes | ||
* '''TDP:''' 70-95 W | * '''TDP:''' 70-95 W | ||
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Mobile {{intel|Coffee Lake|l=arch}} refresh-based Xeon Es were introduced in early 2019. Those models feature higher turbo frequencies as well as a new [[eight-core]] model. All models have the following features in common: | Mobile {{intel|Coffee Lake|l=arch}} refresh-based Xeon Es were introduced in early 2019. Those models feature higher turbo frequencies as well as a new [[eight-core]] model. All models have the following features in common: | ||
− | * ''' | + | * '''CPU:''' [[hexa-core]] with {{intel|Hyper-Threading}}, 12 MiB L3 |
* '''Mem:''' Up to 128 [[GiB]] of dual-channel [[DDR4]] at rates up to 2666 MT/s | * '''Mem:''' Up to 128 [[GiB]] of dual-channel [[DDR4]] at rates up to 2666 MT/s | ||
* '''I/O:''' PCIe Gen 3.0 x16 lanes | * '''I/O:''' PCIe Gen 3.0 x16 lanes | ||
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* '''ISA:''' Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, and AVX2) | * '''ISA:''' Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, and AVX2) | ||
* '''Tech:''' {{intel|Turbo Boost}}, {{intel|VT-x}}, {{intel|VT-d}}, {{intel|EPT}}, {{intel|SpeedStep}} (EIST), {{intel|TXT}}, {{intel|TSX}}, {{intel|vPro}}, Software Guard ({{intel|SGX}}), {{intel|Secure Key}}, Memory Protection ({{intel|MPX}}), {{intel|OS Guard}}, Identity Protection ({{intel|IPT}}), {{intel|SIPP}} | * '''Tech:''' {{intel|Turbo Boost}}, {{intel|VT-x}}, {{intel|VT-d}}, {{intel|EPT}}, {{intel|SpeedStep}} (EIST), {{intel|TXT}}, {{intel|TSX}}, {{intel|vPro}}, Software Guard ({{intel|SGX}}), {{intel|Secure Key}}, Memory Protection ({{intel|MPX}}), {{intel|OS Guard}}, Identity Protection ({{intel|IPT}}), {{intel|SIPP}} | ||
− | * '''GPU:''' {{intel|UHD Graphics 630}} @ 350 MHz with bursts of 1.2 | + | * '''GPU:''' {{intel|UHD Graphics 630}} @ 350 MHz with bursts of 1.2 GHz |
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This table is generated automatically from the data in the actual articles. | This table is generated automatically from the data in the actual articles. |
Facts about "Xeon E - Intel"
designer | Intel + |
first announced | 2018 + |
first launched | 2018 + |
full page name | intel/xeon e + |
instance of | microprocessor family + |
instruction set architecture | x86-64 + |
main designer | Intel + |
manufacturer | Intel + |
microarchitecture | Coffee Lake + |
name | Xeon E + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |