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| title = Intel Xeon D | | title = Intel Xeon D | ||
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| microarch 2 = Skylake (server) | | microarch 2 = Skylake (server) | ||
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'''Xeon D''' is a family of {{arch|64}} multi-core [[x86]] [[microserver]] single-chip processors introduced by [[Intel]] in March of 2015. Xeon D chips are aimed at filling the gap between the {{intel|Atom}} and the {{intel|Xeon E3}} families. Targeting the low-end server market, the Xeon D family puts priority on efficiency and networking - areas where dense, lower-power, lightweight [[hyperscale]] workloads are expected. | '''Xeon D''' is a family of {{arch|64}} multi-core [[x86]] [[microserver]] single-chip processors introduced by [[Intel]] in March of 2015. Xeon D chips are aimed at filling the gap between the {{intel|Atom}} and the {{intel|Xeon E3}} families. Targeting the low-end server market, the Xeon D family puts priority on efficiency and networking - areas where dense, lower-power, lightweight [[hyperscale]] workloads are expected. | ||
== History == | == History == | ||
The Xeon D began as a joint collaboration between [[Facebook]] and [[Intel]] in 2013. Yosemite is the codename for Facebook's open source modular chassis for the highly-concurrent but lower-power microservers. The design calls for dense nodes of lower power but highly concurrent workload which tends to be mostly memory-bandwidth-bound. While early designs where mostly based on the {{intel|Atom}} SoCs, their performance proved to be too much of a bottleneck on its own. Xeon D is a middle-tier family that's a step above {{intel|Atom}} in terms of performance, but below {{intel|Xeon E3}} power-wise. Xeon D is largely driven by high concurrency and better memory capabilities. | The Xeon D began as a joint collaboration between [[Facebook]] and [[Intel]] in 2013. Yosemite is the codename for Facebook's open source modular chassis for the highly-concurrent but lower-power microservers. The design calls for dense nodes of lower power but highly concurrent workload which tends to be mostly memory-bandwidth-bound. While early designs where mostly based on the {{intel|Atom}} SoCs, their performance proved to be too much of a bottleneck on its own. Xeon D is a middle-tier family that's a step above {{intel|Atom}} in terms of performance, but below {{intel|Xeon E3}} power-wise. Xeon D is largely driven by high concurrency and better memory capabilities. | ||
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{| class="wikitable" | {| class="wikitable" | ||
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! Series !! Introduction !! Codename !! Microarchitecture | ! Series !! Introduction !! Codename !! Microarchitecture | ||
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|- | |- | ||
| D-1500 || March, [[2015]] || {{intel|Broadwell DE|l=core}} || {{intel|Broadwell|l=arch}} | | D-1500 || March, [[2015]] || {{intel|Broadwell DE|l=core}} || {{intel|Broadwell|l=arch}} | ||
|- | |- | ||
− | | D- | + | | D-2100 || February, [[2018]] || {{intel|Skylake DE|l=core}} || {{intel|Skylake (server)|Skylake|l=arch}} |
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|- | |- | ||
− | | D- | + | | D-??00 || February, [[2019]] || {{intel|Hewitt Lake|l=core}} || {{intel|Cascade Lake|l=arch}} |
|} | |} | ||
− | == | + | == Members == |
=== D-1500 Series (Broadwell) === | === D-1500 Series (Broadwell) === | ||
[[File:Intel-Xeon-processor-D-1500.png|right|300px]] | [[File:Intel-Xeon-processor-D-1500.png|right|300px]] | ||
− | {{main|intel/microarchitectures/broadwell | + | {{main|intel/microarchitectures/broadwell|l1=Broadwell µarch}} |
− | + | The Xeon D SoCs, which are based on the {{intel|Broadwell DE|l=core}} core, are fabricated a [[14 nm process]] and have started shipping in early 2015. | |
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− | <table class="comptable sortable tc4 tc5 | + | <table class="comptable sortable tc4 tc5"> |
− | {{comp table header|main| | + | {{comp table header|main|7:List of Broadwell-based Xeon D Processors}} |
− | {{comp table header|cols | + | {{comp table header|main|7:Main processor}} |
− | + | {{comp table header|cols|Price|Launched|Cores|Threads|%Frequency|%Turbo|%TDP}} | |
− | {{#ask: [[Category:microprocessor models by intel]] [[ | + | {{#ask: [[Category:microprocessor models by intel]] [[microarchitecture::Broadwell]] [[family::Xeon D]] |
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=== D-2100 Series (Skylake) === | === D-2100 Series (Skylake) === | ||
{{main|intel/microarchitectures/skylake (server)|intel/cores/skylake de|l1=Skylake (server) Microarchitecture|l2=Skylake DE core}} | {{main|intel/microarchitectures/skylake (server)|intel/cores/skylake de|l1=Skylake (server) Microarchitecture|l2=Skylake DE core}} | ||
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+ | === Hewitt Lake === | ||
+ | {{main|intel/cores/hewitt lake|l1=Hewitt Lake core}} | ||
+ | Announced in February 2019, Hewitt Lake will be next-generation Xeon D processors. | ||
== See also == | == See also == | ||
* Qualcomm {{qualcomm|Centriq}} | * Qualcomm {{qualcomm|Centriq}} |
Facts about "Xeon D - Intel"
designer | Intel + |
first announced | March 9, 2015 + |
first launched | March 9, 2015 + |
full page name | intel/xeon d + |
instance of | integrated circuit family + |
instruction set architecture | x86-64 + |
main designer | Intel + |
manufacturer | Intel + |
microarchitecture | Broadwell + and Skylake (server) + |
name | Intel Xeon D + |
package | fcBGA-1667 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
socket | BGA-1667 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |