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| {{ic family | | {{ic family |
| | title = Intel Xeon D | | | title = Intel Xeon D |
− | | image = broadwell de (front).png | + | | image = xeon d.png |
− | | image size = 250px | + | | image size = 150px |
| | caption = Xeon D | | | caption = Xeon D |
| | developer = Intel | | | developer = Intel |
| | manufacturer = Intel | | | manufacturer = Intel |
− | | type = System in packages | + | | type = System on chips |
| | first announced = March 9, 2015 | | | first announced = March 9, 2015 |
| | first launched = March 9, 2015 | | | first launched = March 9, 2015 |
| | isa = x86-64 | | | isa = x86-64 |
| | microarch = Broadwell | | | microarch = Broadwell |
− | | microarch 2 = Skylake (server)
| |
| | word = 64 bit | | | word = 64 bit |
| | proc = 14 nm | | | proc = 14 nm |
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| | socket = BGA-1667 | | | socket = BGA-1667 |
| }} | | }} |
− | [[File:broadwell de (back).png|225px|right]] | + | [[File:xeon d (back).png|225px|right]] |
− | '''Xeon D''' is a family of {{arch|64}} multi-core [[x86]] [[microserver]] single-chip processors introduced by [[Intel]] in March of 2015. Xeon D chips are aimed at filling the gap between the {{intel|Atom}} and the {{intel|Xeon E3}} families. Targeting the low-end server market, the Xeon D family puts priority on efficiency and networking - areas where dense, lower-power, lightweight [[hyperscale]] workloads are expected. | + | '''Xeon D''' is a family of {{arch|64}} multi-core [[x86]] [[microserver]] [[system on chip]]s introduced by [[Intel]] in March of 2015. Xeon D chips are aimed at filling the gap between the {{intel|Atom}} and the {{intel|Xeon E3}} families. Targeting the low-end server market, the Xeon D family puts priority on efficiency and networking - areas where dense, lower-power, lightweight [[hyperscale]] workloads are expected. |
| | | |
| == History == | | == History == |
− | The Xeon D began as a joint collaboration between [[Facebook]] and [[Intel]] in 2013. Yosemite is the codename for Facebook's open source modular chassis for the highly-concurrent but lower-power microservers. The design calls for dense nodes of lower power but highly concurrent workload which tends to be mostly memory-bandwidth-bound. While early designs where mostly based on the {{intel|Atom}} SoCs, their performance proved to be too much of a bottleneck on its own. Xeon D is a middle-tier family that's a step above {{intel|Atom}} in terms of performance, but below {{intel|Xeon E3}} power-wise. Xeon D is largely driven by high concurrency and better memory capabilities. | + | The Xeon D began as a joint collaboration between [[Facebook]] and [[Intel]] in 2013. Yosemite is the codename for Facebook's open source modular chassis for the highly-concurrent but lower-power microservers. The design calls dense nodes of lower power but highly concurrent workload which tends to be mostly memory-bandwidth-bound. While early designs where mostly based on the {{intel|Atom}} SoCs, their performance proved to be too much of a bottleneck on its own. Xeon D is a middle-tier family that's a step above {{intel|Atom}} in terms of performance, but below {{intel|Xeon E3}} power-wise. Xeon D will continue to be driven by high concurrency and better memory capabilities. |
| | | |
− | Currently, Intel offers two series of Xeon D parts - dense low-power and dense high-power parts.
| + | In March of 2015 Intel released the first line of Xeon D SoC. Those chips were manufactured in [[14 nm]] and implement the [[intel/microarchitectures/broadwell|Broadwell microarchitecture]]. |
− | | + | == Members == |
− | {| class="wikitable"
| + | === Broadwell DE=== |
− | |-
| |
− | ! Series !! Introduction !! Codename !! Microarchitecture
| |
− | |-
| |
− | ! colspan="4" | Dense, Low-power
| |
− | |-
| |
− | | D-1500 || March, [[2015]] || {{intel|Broadwell DE|l=core}} || {{intel|Broadwell|l=arch}}
| |
− | |-
| |
− | | D-1600 || April, [[2019]] || {{intel|Hewitt Lake|l=core}} || {{intel|Broadwell|l=arch}}
| |
− | |-
| |
− | ! colspan="4" | Dense, High-power
| |
− | |-
| |
− | | D-2100 || February, [[2018]] || {{intel|Skylake DE|l=core}} || {{intel|Skylake (server)|Skylake|l=arch}}
| |
− | |}
| |
− | | |
− | == Dense Low-Power == | |
− | === D-1500 Series (Broadwell) === | |
| [[File:Intel-Xeon-processor-D-1500.png|right|300px]] | | [[File:Intel-Xeon-processor-D-1500.png|right|300px]] |
− | {{main|intel/microarchitectures/broadwell (server)|intel/cores/broadwell de|l1=Broadwell (Server) µarch|l2=Broadwell DE Core}} | + | {{main|intel/microarchitectures/broadwell|l1=Broadwell µarch}} |
− | First-generation of dense low-power Xeon D parts were introduced in early [[2015]] and are based on the {{intel|Broadwell (server)|Broadwell|l=arch}} microarchitecture. Fabricated on their [[14 nm process]], those parts incorporate up to [[16 cores|sixteen cores]] with a [[TDP]] of up to 65 W.
| + | The Xeon D SoCs, which are based on the {{intel|Broadwell DE|l=core}} core, are fabricated a [[14 nm process]] and have started shipping in early 2015. |
− | | |
− | * '''TDP:''' 20-65 W
| |
− | * '''Mem:''' 128 GiB dual-channel DDR4 ECC memory up to 2133/2400 MT/s. (128 GiB @ [[RDIMM]] 32 GiB/DIMM, 64 GiB @ UDIMM/SODIMM 16 GiB/DIMM)
| |
− | * '''I/O:''' 32 PCIe 3/2 lanes (x24 Gen3 + x8 Gen2)
| |
− | * '''ISA:''' Everything up to {{x86|AVX2}} ({{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}})
| |
− | * '''Features:''' {{intel|SpeedStep}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Secure Key}}, and {{intel|OS Guard}}
| |
| | | |
− | All models are a single-chip solution, meaning both the [[CPU]] [[die]] and the [[chipset]] die are packaged together on the same substrate.
| |
| <!-- NOTE: | | <!-- NOTE: |
| This table is generated automatically from the data in the actual articles. | | This table is generated automatically from the data in the actual articles. |
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| created and tagged accordingly. | | created and tagged accordingly. |
| | | |
− | Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips | + | Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips |
| --> | | --> |
− | {{comp table start}}
| + | <table class="wikitable sortable"> |
− | <table class="comptable sortable tc4 tc5 tc11"> | + | <tr><th colspan="12" style="background:#D6D6FF;">Broadwell-based Xeon D</th></tr> |
− | {{comp table header|main|11:List of Broadwell DE-based Processors}}
| + | <tr><th colspan="9">Main processor</th></tr> |
− | {{comp table header|cols|Launched|Price|C|T|TDP|L2|L3|%Frequency|%Turbo|QAT}}
| + | <tr><th>Model</th><th>Launched</th><th>Cores</th><th>Threads</th><th>Freq</th><th>Turbo Freq</th><th>TDP</th><th>Max Mem</th></tr> |
− | {{comp table header|lsep|11:Edge Server and Cloud SKUs}}
| + | {{#ask: [[Category:microprocessor models by intel]][[instance of::microprocessor]][[microprocessor family::Xeon D]] |
− | {{#ask: [[Category:microprocessor models by intel]] [[core name::Broadwell DE]] [[model number ::!~*N]] | |
| |?full page name | | |?full page name |
| |?model number | | |?model number |
| |?first launched | | |?first launched |
− | |?release price
| |
| |?core count | | |?core count |
| |?thread count | | |?thread count |
− | |?tdp
| |
− | |?l2$ size
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− | |?l3$ size
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| |?base frequency#GHz | | |?base frequency#GHz |
| |?turbo frequency (1 core)#GHz | | |?turbo frequency (1 core)#GHz |
− | |?has integrated intel quickassist technology
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− | |format=template
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− | |template=proc table 3
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− | |userparam=12:12
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− | |sort=model number
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− | |mainlabel=-
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− | }}
| |
− | {{comp table header|lsep|11:Network Edge and Storage SKUs}}
| |
− | {{#ask: [[Category:microprocessor models by intel]] [[core name::Broadwell DE]] [[model number ::~*N]]
| |
− | |?full page name
| |
− | |?model number
| |
− | |?first launched
| |
− | |?release price
| |
− | |?core count
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− | |?thread count
| |
| |?tdp | | |?tdp |
− | |?l2$ size | + | |?max memory#GB |
− | |?l3$ size
| |
− | |?base frequency#GHz
| |
− | |?turbo frequency (1 core)#GHz
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− | |?has integrated intel quickassist technology
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− | |format=template
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− | |template=proc table 3
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− | |userparam=12:12
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− | |sort=model number
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− | |mainlabel=-
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− | }}
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− | {{comp table count|ask=[[Category:microprocessor models by intel]] [[core name::Broadwell DE]]}}
| |
− | </table>
| |
− | {{comp table end}}
| |
− | | |
− | ==== Documents ====
| |
− | * [[:File:xeon d-1500-brief.pdf|Product Brief - Intel® Xeon® Processor D-1500 Product Family - Extending Intelligence to the Edge]]
| |
− | * [[:File:xeon d-1500-brief (1).pdf|Product Brief - Intel® Xeon® Processor D-1500 Product Family - Extending Intelligence to the Edge (2)]]
| |
− | * [[:File:xeon d-1500-platform-brief.pdf|Platform Brief - Intel® Xeon® Processor D-1500 Product Family]]
| |
− | | |
− | === D-1600 Series (Hewitt Lake) ===
| |
− | [[File:hewitt lake (front).png|thumb|right|200px|Hewitt Lake is branded as D-1600 series.]]
| |
− | {{main|intel/cores/hewitt lake|l1=Hewitt Lake core}}
| |
− | Intel introduced a refresh of the {{intel|Broadwell DE|l=core}} in early 2019, formerly codename {{intel|Hewitt Lake|l=core}}. Like the prior generation, those new processors are also based on the {{intel|Broadwell (server)|Broadwell|l=arch}} microarchitecture. Fabricated on their [[14 nm process]], those parts incorporate up to [[16 cores|sixteen cores]] with a [[TDP]] of up to 65 W. The new SKUs feature higher frequencies at similar TDPs, improving the performance per watt.
| |
− | | |
− | * '''TDP:''' 22-65 W
| |
− | * '''Mem:''' 128 GiB dual-channel DDR4 ECC memory up to 2133/2400 MT/s. (128 GiB @ [[RDIMM]] 32 GiB/DIMM, 64 GiB @ UDIMM/SODIMM 16 GiB/DIMM)
| |
− | * '''I/O:''' 32 PCIe 3/2 lanes (x24 Gen3 + x8 Gen2)
| |
− | * '''ISA:''' Everything up to {{x86|AVX2}} ({{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}})
| |
− | * '''Features:''' {{intel|SpeedStep}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Secure Key}}, and {{intel|OS Guard}}
| |
− | | |
− | All models are a single-chip solution, meaning both the [[CPU]] [[die]] and the [[chipset]] die are packaged together on the same substrate.
| |
− | <!-- NOTE:
| |
− | This table is generated automatically from the data in the actual articles.
| |
− | If a microprocessor is missing from the list, an appropriate article for it needs to be
| |
− | created and tagged accordingly.
| |
− | | |
− | Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
| |
− | -->
| |
− | {{comp table start}}
| |
− | <table class="comptable sortable tc4 tc5 tc11">
| |
− | {{comp table header|main|11:List of Hewitt Lake-based Processors}}
| |
− | {{comp table header|cols|Launched|Price|C|T|TDP|L2|L3|%Frequency|%Turbo|QAT}}
| |
− | {{comp table header|lsep|11:Edge Server and Cloud SKUs}}
| |
− | {{#ask: [[Category:microprocessor models by intel]] [[core name::Hewitt Lake]] [[model number ::!~*N]]
| |
− | |?full page name
| |
− | |?model number
| |
− | |?first launched
| |
− | |?release price
| |
− | |?core count
| |
− | |?thread count
| |
− | |?tdp
| |
− | |?l2$ size
| |
− | |?l3$ size
| |
− | |?base frequency#GHz
| |
− | |?turbo frequency (1 core)#GHz
| |
− | |?has integrated intel quickassist technology
| |
− | |format=template
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− | |template=proc table 3
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− | |userparam=12:12
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− | |sort=model number
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− | |mainlabel=-
| |
− | }}
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− | {{comp table header|lsep|11:Network Edge and Storage SKUs}}
| |
− | {{#ask: [[Category:microprocessor models by intel]] [[core name::Hewitt Lake]] [[model number ::~*N]]
| |
− | |?full page name
| |
− | |?model number
| |
− | |?first launched
| |
− | |?release price
| |
− | |?core count
| |
− | |?thread count
| |
− | |?tdp
| |
− | |?l2$ size
| |
− | |?l3$ size
| |
− | |?base frequency#GHz
| |
− | |?turbo frequency (1 core)#GHz
| |
− | |?has integrated intel quickassist technology
| |
− | |format=template
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− | |template=proc table 3
| |
− | |userparam=12:12
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− | |sort=model number
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− | |mainlabel=-
| |
− | }}
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− | {{comp table count|ask=[[Category:microprocessor models by intel]] [[core name::Hewitt Lake]]}}
| |
− | </table>
| |
− | {{comp table end}}
| |
− | | |
− | == Dense High-Power ==
| |
− | === D-2100 Series (Skylake) ===
| |
− | {{main|intel/microarchitectures/skylake (server)|intel/cores/skylake de|l1=Skylake (server) Microarchitecture|l2=Skylake DE core}}
| |
− | Introduced in February [[2018]], Xeon D-2100 series processors are based on the {{intel|Skylake (server)|Skylake microarchitecture|l=arch}}. Those low-power variant range from [[4 cores|4]] to [[18 cores]] with {{intel|hyperthreading}} support. As with the previous generations, those chips are also a single-chip solution - the {{intel|Lewisburg|l=chipset}} [[chipset]] is incorporated into the same package as the processor. Being based on the new {{intel|Skylake (server)|Skylake microarchitecture|l=arch}} means those parts are also based on the mesh architecture which brought a much bigger L2 cache and supports twice as many memory channels. Additionally, all models also support {{x86|AVX-512}} with a single execution unit.
| |
− | | |
− | SKUs are suffixed with either I, T, and N or combination of multiple of those options:
| |
− | | |
− | * '''I''' - Integrated Ethernet
| |
− | * '''T''' - High Temperature (90° [[tcase|T<sub>CASE</sub>]]) and extended reliability support
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− | * '''N''' - Integrated Ethernet and Intel's {{intel|QuickAssist}} technology
| |
− | | |
− | All models have all the following features in common:
| |
− | | |
− | * '''Mem:''' Up 512 GiB of quad-channel DDR4 Memory
| |
− | ** DPC RDIMM and LRDIMM \w [[ECC]]
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− | * '''I/O:''' 32 [[PCIe]] 3.0 Lanes + 20 configurable High-Speed I/O (HSIO) lanes
| |
− | * '''TDP:''' < 110 W
| |
− | * '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX512F, AVX512CD, AVX512BW, AVX512DQ, AVX512VL)
| |
− | * '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}/{{intel|EPT}}, {{intel|VT-d}}, {{intel|TBT 2.0}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|SpeedStep}}, {{intel|Secure Key}}, {{intel|MPX}}, {{intel|OS Guard}}, and {{intel|RAS}}.
| |
− | | |
− | <!-- NOTE:
| |
− | This table is generated automatically from the data in the actual articles.
| |
− | If a microprocessor is missing from the list, an appropriate article for it needs to be
| |
− | created and tagged accordingly.
| |
− | | |
− | Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
| |
− | -->
| |
− | {{comp table start}}
| |
− | <table class="comptable sortable tc4 tc5 tc12">
| |
− | {{comp table header|main|11:List of Skylake DE-based Processors}}
| |
− | {{comp table header|cols|Launched|Price|Cores|Threads|TDP|L2|L3|%Frequency|%Turbo|Memory|QAT}}
| |
− | {{comp table header|lsep|11:Edge Server and Cloud SKUs}}
| |
− | {{#ask: [[Category:microprocessor models by intel]] [[core name::Skylake DE]] [[part of::Edge Server and Cloud SKUs]]
| |
− | |?full page name
| |
− | |?model number
| |
− | |?first launched
| |
− | |?release price
| |
− | |?core count
| |
− | |?thread count
| |
− | |?tdp
| |
− | |?l2$ size
| |
− | |?l3$ size
| |
− | |?base frequency#GHz
| |
− | |?turbo frequency (1 core)#GHz
| |
− | |?supported memory type
| |
− | |?has integrated intel quickassist technology
| |
− | |format=template
| |
− | |template=proc table 3
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− | |userparam=13:13
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− | |sort=model number
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− | |mainlabel=-
| |
− | }}
| |
− | {{comp table header|lsep|11:Network Edge and Storage SKUs}}
| |
− | {{#ask: [[Category:microprocessor models by intel]] [[core name::Skylake DE]] [[part of::Network Edge and Storage SKUs]]
| |
− | |?full page name
| |
− | |?model number
| |
− | |?first launched
| |
− | |?release price
| |
− | |?core count
| |
− | |?thread count
| |
− | |?tdp
| |
− | |?l2$ size
| |
− | |?l3$ size
| |
− | |?base frequency#GHz
| |
− | |?turbo frequency (1 core)#GHz
| |
− | |?supported memory type
| |
− | |?has integrated intel quickassist technology
| |
− | |format=template
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− | |template=proc table 3
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− | |userparam=13:13
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− | |sort=model number
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− | |mainlabel=-
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− | }}
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− | {{comp table header|lsep|11:Integrated QuickAssist Technology SKUs}}
| |
− | {{#ask: [[Category:microprocessor models by intel]] [[core name::Skylake DE]] [[part of::Integrated QuickAssist Technology SKUs]]
| |
− | |?full page name
| |
− | |?model number
| |
− | |?first launched
| |
− | |?release price
| |
− | |?core count
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− | |?thread count
| |
− | |?tdp
| |
− | |?l2$ size
| |
− | |?l3$ size
| |
− | |?base frequency#GHz
| |
− | |?turbo frequency (1 core)#GHz
| |
− | |?supported memory type
| |
− | |?has integrated intel quickassist technology
| |
| |format=template | | |format=template |
− | |template=proc table 3 | + | |template=proc table 2 |
− | |userparam=13:13 | + | |userparam=9 |
− | |sort=model number
| |
| |mainlabel=- | | |mainlabel=- |
| }} | | }} |
− | {{comp table count|ask=[[Category:microprocessor models by intel]] [[core name::Skylake DE]]}} | + | <tr><th colspan="12">Count: {{#ask:[[Category:microprocessor models by intel]][[instance of::microprocessor]][[microprocessor family::Xeon D]]|format=count}}</th></tr> |
| </table> | | </table> |
− | {{comp table end}}
| |
| | | |
| == See also == | | == See also == |
| * Qualcomm {{qualcomm|Centriq}} | | * Qualcomm {{qualcomm|Centriq}} |