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=== D-1600 Series (Hewitt Lake) === | === D-1600 Series (Hewitt Lake) === | ||
− | [[File:hewitt lake (front).png|thumb|right | + | [[File:hewitt lake (front).png|thumb|right|Hewitt Lake is branded as D-1600 series.]] |
{{main|intel/cores/hewitt lake|l1=Hewitt Lake core}} | {{main|intel/cores/hewitt lake|l1=Hewitt Lake core}} | ||
Intel introduced a refresh of the {{intel|Broadwell DE|l=core}} in early 2019, formerly codename {{intel|Hewitt Lake|l=core}}. Like the prior generation, those new processors are also based on the {{intel|Broadwell (server)|Broadwell|l=arch}} microarchitecture. Fabricated on their [[14 nm process]], those parts incorporate up to [[16 cores|sixteen cores]] with a [[TDP]] of up to 65 W. The new SKUs feature higher frequencies at similar TDPs, improving the performance per watt. | Intel introduced a refresh of the {{intel|Broadwell DE|l=core}} in early 2019, formerly codename {{intel|Hewitt Lake|l=core}}. Like the prior generation, those new processors are also based on the {{intel|Broadwell (server)|Broadwell|l=arch}} microarchitecture. Fabricated on their [[14 nm process]], those parts incorporate up to [[16 cores|sixteen cores]] with a [[TDP]] of up to 65 W. The new SKUs feature higher frequencies at similar TDPs, improving the performance per watt. |
Facts about "Xeon D - Intel"
designer | Intel + |
first announced | March 9, 2015 + |
first launched | March 9, 2015 + |
full page name | intel/xeon d + |
instance of | integrated circuit family + |
instruction set architecture | x86-64 + |
main designer | Intel + |
manufacturer | Intel + |
microarchitecture | Broadwell + and Skylake (server) + |
name | Intel Xeon D + |
package | fcBGA-1667 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
socket | BGA-1667 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |