Editing intel/xeon d/d-2161i

{{intel title|Xeon D-2161I}}
{{chip
|name=Xeon D-2161I
|image=skylake-de (front).png
|designer=Intel
|manufacturer=Intel
|model number=D-2161I
|part number=FH8067303534104
|s-spec=SR3ZN
|market=Server
|market 2=Embedded
|first announced=February 7, 2018
|first launched=February 7, 2018
|release price=$962.00
|family=Xeon D
|series=D-2000
|locked=Yes
|frequency=2,200 MHz
|turbo frequency1=3,000 MHz
|bus type=DMI 3.0
|bus links=4
|bus rate=8 GT/s
|clock multiplier=22
|isa=x86-64
|isa family=x86
|microarch=Skylake (server)
|core name=Skylake DE
|core stepping=M1
|process=14 nm
|technology=CMOS
|mcp=Yes
|die count=2
|word size=64 bit
|core count=12
|thread count=24
|max cpus=1
|max memory=512 GiB
|tdp=90 W
|package module 1={{packages/intel/fcbga-2518}}
}}
'''Xeon D-2161I''' is a {{arch|64}} [[12-core]] high-performance [[x86]] server microprocessor introduced by [[Intel]] in early 2018 for the dense server and [[edge computing]] market segment. Fabricated on Intel's [[14 nm process]] based on the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture, this model operates at 2.2 GHz with a {{intel|Turbo Boost}} of up to 3.0 GHz and a [[TDP]] of 90 W. The D-2161I supports up to 512 GiB of quad-chanel DDR4-2133 ECC memory. This model is part of {{intel|Skylake DE|l=core}}'s [[part of::Edge Server and Cloud SKUs]].


{{unknown features}}


== Cache ==
{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
{{cache size
|l1 cache=768 KiB
|l1i cache=384 KiB
|l1i break=12x32 KiB
|l1i desc=8-way set associative
|l1d cache=384 KiB
|l1d break=12x32 KiB
|l1d desc=8-way set associative
|l1d policy=write-back
|l2 cache=12 MiB
|l2 break=12x1 MiB
|l2 desc=16-way set associative
|l2 policy=write-back
|l3 cache=16.5 MiB
|l3 break=12x1.375 MiB
|l3 desc=11-way set associative
|l3 policy=write-back
}}

== Memory controller ==
{{memory controller
|type=DDR4-2133
|ecc=Yes
|max mem=512 GiB
|controllers=2
|channels=4
|max bandwidth=79.47 GiB/s
|bandwidth schan=15.89 GiB/s
|bandwidth dchan=31.78 GiB/s
|bandwidth qchan=63.57 GiB/s
|pae=46 bit
}}

== Expansions ==
This chip incorporates 20 high-speed I/O (HSIO) lanes that may be configured as up to 20 [[PCIe]] lanes, up to 14 SATA 3.0 ports, or up to 4 USB 3.0 ports.
{{expansions main
|
{{expansions entry
|type=PCIe
|pcie revision=3.0
|pcie lanes=32
|pcie config=x16
|pcie config 2=x8
|pcie config 3=x4
}}
{{expansions entry
|type=HSIO
|hsio lanes=20
}}
}}
== Networking ==
{{network
|eth opts=Yes
|10ge=Yes
|10ge ports=4
}}
== Features == 
{{x86 features
|real=Yes
|protected=Yes
|smm=Yes
|fpu=Yes
|x8616=Yes
|x8632=Yes
|x8664=Yes
|nx=Yes
|mmx=Yes
|emmx=Yes
|sse=Yes
|sse2=Yes
|sse3=Yes
|ssse3=Yes
|sse41=Yes
|sse42=Yes
|sse4a=No
|avx=Yes
|avx2=Yes
|avx512f=Yes
|avx512cd=Yes
|avx512er=No
|avx512pf=No
|avx512bw=Yes
|avx512dq=Yes
|avx512vl=Yes
|avx512ifma=No
|avx512vbmi=No
|avx5124fmaps=No
|avx5124vnniw=No
|avx512vpopcntdq=No
|avx512units=1
|abm=Yes
|tbm=No
|bmi1=Yes
|bmi2=Yes
|fma3=Yes
|fma4=No
|aes=Yes
|rdrand=Yes
|sha=No
|xop=No
|adx=Yes
|clmul=Yes
|f16c=Yes
|tbt1=No
|tbt2=Yes
|tbmt3=No
|bpt=No
|eist=Yes
|sst=Yes
|flex=No
|fastmem=No
|ivmd=Yes
|intelnodecontroller=No
|intelnode=No
|kpt=No
|ptt=No
|intelrunsure=No
|mbe=No
|isrt=No
|sba=No
|mwt=No
|sipp=No
|att=No
|ipt=Yes
|tsx=Yes
|txt=Yes
|ht=Yes
|vpro=Yes
|vtx=Yes
|vtd=Yes
|ept=Yes
|mpx=Yes
|sgx=No
|securekey=Yes
|osguard=Yes
|intqat=No
|3dnow=No
|e3dnow=No
|smartmp=No
|powernow=No
|amdvi=No
|amdv=No
|amdsme=No
|amdtsme=No
|amdsev=No
|rvi=No
|smt=No
|sensemi=No
|xfr=No
|mxfr=No
|amdpb=No
|amdpb2=No
}}

== Frequencies ==
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
{{frequency table
|freq_base=2,200 MHz
|freq_1=3,000 MHz
|freq_2=3,000 MHz
|freq_3=2,800 MHz
|freq_4=2,800 MHz
|freq_5=2,800 MHz
|freq_6=2,800 MHz
|freq_7=2,800 MHz
|freq_8=2,800 MHz
|freq_9=2,800 MHz
|freq_10=2,800 MHz
|freq_11=2,800 MHz
|freq_12=2,800 MHz
|freq_avx2_1=2,900 MHz
|freq_avx2_2=2,900 MHz
|freq_avx2_3=2,700 MHz
|freq_avx2_4=2,700 MHz
|freq_avx2_5=2,700 MHz
|freq_avx2_6=2,700 MHz
|freq_avx2_7=2,700 MHz
|freq_avx2_8=2,700 MHz
|freq_avx2_9=2,700 MHz
|freq_avx2_10=2,700 MHz
|freq_avx2_11=2,700 MHz
|freq_avx2_12=2,700 MHz
|freq_avx512_1=2,800 MHz
|freq_avx512_2=2,800 MHz
|freq_avx512_3=2,600 MHz
|freq_avx512_4=2,600 MHz
|freq_avx512_5=2,500 MHz
|freq_avx512_6=2,500 MHz
|freq_avx512_7=2,500 MHz
|freq_avx512_8=2,500 MHz
|freq_avx512_9=2,200 MHz
|freq_avx512_10=2,200 MHz
|freq_avx512_11=2,200 MHz
|freq_avx512_12=2,200 MHz
}}
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon D-2161I - Intel#package + and Xeon D-2161I - Intel#pcie +
base frequency	2,200 MHz (2.2 GHz, 2,200,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
clock multiplier	22 +
core count	12 +
core name	Skylake DE +
core stepping	M1 +
designer	Intel +
die count	2 +
family	Xeon D +
first announced	February 7, 2018 +
first launched	February 7, 2018 +
full page name	intel/xeon d/d-2161i +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Encryption Standard Instruction Set Extension +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Enhanced SpeedStep Technology +, Extended Page Tables +, Hyper-Threading Technology +, Identity Protection Technology +, Intel VT-d +, Intel VT-x +, Intel vPro Technology +, Memory Protection Extensions +, OS Guard +, Secure Key Technology +, Speed Shift Technology +, Transactional Synchronization Extensions +, Trusted Execution Technology + and Turbo Boost Technology 2.0 +
has intel enhanced speedstep technology	true +
has intel identity protection technology support	true +
has intel secure key technology	true +
has intel speed shift technology	true +
has intel supervisor mode execution protection	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
is multi-chip package	true +
isa	x86-64 +
isa family	x86 +
l1$ size	768 KiB (786,432 B, 0.75 MiB) +
l1d$ description	8-way set associative +
l1d$ size	384 KiB (393,216 B, 0.375 MiB) +
l1i$ description	8-way set associative +
l1i$ size	384 KiB (393,216 B, 0.375 MiB) +
l2$ description	16-way set associative +
l2$ size	12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
l3$ description	11-way set associative +
l3$ size	16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) +
ldate	February 7, 2018 +
main image	+
manufacturer	Intel +
market segment	Embedded + and Server +
max cpu count	1 +
max hsio lanes	20 +
max memory	524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) +
max memory bandwidth	79.47 GiB/s (81,377.28 MiB/s, 85.33 GB/s, 85,330.263 MB/s, 0.0776 TiB/s, 0.0853 TB/s) +
max memory channels	4 +
microarchitecture	Skylake (server) +
model number	D-2161I +
name	Xeon D-2161I +
number of avx-512 execution units	1 +
package	FCBGA-2518 +
part number	FH8067303534104 +
part of	Edge Server and Cloud SKUs +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 962.00 (€ 865.80, £ 779.22, ¥ 99,403.46) +
s-spec	SR3ZN +
series	D-2000 +
smp max ways	1 +
supported memory type	DDR4-2133 +
tdp	90 W (90,000 mW, 0.121 hp, 0.09 kW) +
technology	CMOS +
thread count	24 +
turbo frequency (1 core)	3,000 MHz (3 GHz, 3,000,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensions	true +