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− | '''Xeon Bronze''' is a family of {{arch|64}} [[x86]] dual-socket multi-core entry-level server | + | '''Xeon Bronze''' is a family of {{arch|64}} [[x86]] dual-socket multi-core entry-level server microprocessors introduced by [[Intel]] in 2017. |
== Overview == | == Overview == | ||
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== Members == | == Members == | ||
− | === | + | === Skylake === |
{{see also|intel/microarchitectures/skylake (server)|l1=Skylake µarch}} | {{see also|intel/microarchitectures/skylake (server)|l1=Skylake µarch}} | ||
− | + | Introduced in July 2017, the {{intel|Skylake (server)|Skylake|l=arch}}-based Xeon Bronze microprocessors are all dual-socket multiprocessors with up to [[8 cores]] and 8 threads. Additionally, all Xeon Bronze processors support: | |
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* '''TDP:''' 85 W | * '''TDP:''' 85 W | ||
* '''Mem:''' 768 GiB hexa-channel DDR4-2133 ECC memory. | * '''Mem:''' 768 GiB hexa-channel DDR4-2133 ECC memory. | ||
− | * '''I/O:''' 48 PCIe | + | * '''I/O:''' 48 PCIe 3 lanes |
− | * '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, | + | * '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX512F, AVX512CD, AVX512BW, AVX512DQ, AVX512VL) |
* '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT). | * '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT). | ||
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{{comp table start}} | {{comp table start}} | ||
<table class="comptable sortable tc4 tc5"> | <table class="comptable sortable tc4 tc5"> | ||
− | + | <tr class="comptable-header"><th> </th><th colspan="20">List of Skylake-based Xeon Bronze Processors</th></tr> | |
− | {{comp table header 1|cols=Price, Launched, Cores, Threads, Frequency, TDP, L2$, L3$}} | + | <tr class="comptable-header"><th> </th><th colspan="6">Main processor</th><th colspan="2">Cache</th><th colspan="2">Memory</th></tr> |
+ | {{comp table header 1|cols=Price, Launched, Cores, Threads, Frequency, TDP, L2$, L3$, Mem Type, Max Mem}} | ||
{{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Bronze]] [[microarchitecture::Skylake (server)]] | {{#ask: [[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Bronze]] [[microarchitecture::Skylake (server)]] | ||
|?full page name | |?full page name | ||
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|?l2$ size | |?l2$ size | ||
|?l3$ size | |?l3$ size | ||
+ | |?supported memory type | ||
+ | |?max memory#GiB | ||
|format=template | |format=template | ||
|template=proc table 3 | |template=proc table 3 | ||
− | |userparam= | + | |userparam=12 |
|mainlabel=- | |mainlabel=- | ||
}} | }} | ||
{{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Bronze]] [[microarchitecture::Skylake (server)]]}} | {{comp table count|ask=[[Category:microprocessor models by intel]] [[instance of::microprocessor]] [[microprocessor family::Xeon Bronze]] [[microarchitecture::Skylake (server)]]}} | ||
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</table> | </table> | ||
{{comp table end}} | {{comp table end}} |
Facts about "Xeon Bronze - Intel"
designer | Intel + |
first announced | May 4, 2017 + |
first launched | July 11, 2017 + |
full page name | intel/xeon bronze + |
instance of | microprocessor family + |
instruction set architecture | x86-64 + |
main designer | Intel + |
manufacturer | Intel + |
microarchitecture | Skylake + |
name | Xeon Bronze + |
package | FCLGA-3647 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
socket | LGA-3647 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |