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|introduction=2020 | |introduction=2020 | ||
|process=10 nm | |process=10 nm | ||
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|isa=x86-64 | |isa=x86-64 | ||
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|predecessor=Sunny Cove | |predecessor=Sunny Cove | ||
|predecessor link=intel/microarchitectures/sunny cove | |predecessor link=intel/microarchitectures/sunny cove | ||
|successor=Golden Cove | |successor=Golden Cove | ||
|successor link=intel/microarchitectures/golden cove | |successor link=intel/microarchitectures/golden cove | ||
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}} | }} | ||
'''Willow Cove''' is the successor to {{\\|Sunny Cove}}, a high-performance [[10 nm]] [[x86]] core microarchitecture designed by [[Intel]] for an array of server and client products, including {{\\|Tiger Lake}}. | '''Willow Cove''' is the successor to {{\\|Sunny Cove}}, a high-performance [[10 nm]] [[x86]] core microarchitecture designed by [[Intel]] for an array of server and client products, including {{\\|Tiger Lake}}. | ||
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== Process Technology == | == Process Technology == | ||
− | Willow Cove is designed to take advantage of Intel's [[10 nm process]] | + | Willow Cove is designed to take advantage of Intel's [[10 nm process]]. |
== Architecture == | == Architecture == | ||
Key changes from {{\\|Sunny Cove}} | Key changes from {{\\|Sunny Cove}} | ||
− | * Expanded L2 Cache ( | + | * Expanded L2 Cache(From {{\\|Sunny Cove}}'s 512kb 8-way to 1.25MB 20-way) |
− | * 50% Expanded L3 Cache ( | + | * 50% Expanded L3 Cache (From {{\\|Sunny Cove}}'s 8mb 16-way to 12mb 12-way) |
− | * | + | * Security features |
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{{expand list}} | {{expand list}} | ||
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* Additional {{x86|AVX-512}} extensions: | * Additional {{x86|AVX-512}} extensions: | ||
** {{x86|AVX512_VP2INTERSECT|<code>AVX512_VP2INTERSECT</code>}} - AVX-512 Vector Intersection Instructions | ** {{x86|AVX512_VP2INTERSECT|<code>AVX512_VP2INTERSECT</code>}} - AVX-512 Vector Intersection Instructions | ||
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+ | ''Only on server parts ({{\\|Sapphire Rapids}}):'' | ||
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+ | * {{x86|ENQCMD|<code>ENQCMD</code>}} - Enqueue Stores | ||
+ | * Intel Advanced Matrix Extensions (Intel AMX) | ||
== Bibliography == | == Bibliography == | ||
* Intel Architecture Day 2018, December 11, 2018 | * Intel Architecture Day 2018, December 11, 2018 |
Facts about "Willow Cove - Microarchitectures - Intel"
codename | Willow Cove + |
core count | 2 +, 4 +, 6 + and 8 + |
designer | Intel + |
first launched | 2020 + |
full page name | intel/microarchitectures/willow cove + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Willow Cove + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |