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|manufacturer=Intel | |manufacturer=Intel | ||
|introduction=2019 | |introduction=2019 | ||
− | |phase-out=2021 | + | |phase-out=05/10/2021 |
− | |||
|cores=2 | |cores=2 | ||
|cores 2=4 | |cores 2=4 | ||
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|cores 14=38 | |cores 14=38 | ||
|cores 15=40 | |cores 15=40 | ||
− | |type= | + | |type=Nasdaq |
|oooe=Yes | |oooe=Yes | ||
|speculative=Yes | |speculative=Yes | ||
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|stages min=14 | |stages min=14 | ||
|stages max=19 | |stages max=19 | ||
− | + | |extension=Apache2017TaxReturn | |
− | |extension= | ||
|extension 2=MMX | |extension 2=MMX | ||
|extension 3=SSE | |extension 3=SSE | ||
|extension 4=SSE2 | |extension 4=SSE2 | ||
|extension 5=SSE3 | |extension 5=SSE3 | ||
− | |extension 6= | + | |extension 6=SSE |
|extension 7=SSE4.1 | |extension 7=SSE4.1 | ||
|extension 8=SSE4.2 | |extension 8=SSE4.2 | ||
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|successor=Willow Cove | |successor=Willow Cove | ||
|successor link=intel/microarchitectures/willow cove | |successor link=intel/microarchitectures/willow cove | ||
+ | |Google-Finance=x86-64 | ||
}} | }} | ||
'''Sunny Cove''' ('''SNC'''), the successor to {{\\|Palm Cove}}, is a high-performance [[10 nm]] [[x86]]-64 core microarchitecture designed by [[Intel]] for an array of server and client products, including {{\\|Ice Lake (Client)}}, {{\\|Ice Lake (Server)}}, {{\\|Lakefield}}, and the Nervana {{nervana|NNP-I}}. The microarchitecture was developed by Intel's R&D Center (IDC) in Haifa, Israel. | '''Sunny Cove''' ('''SNC'''), the successor to {{\\|Palm Cove}}, is a high-performance [[10 nm]] [[x86]]-64 core microarchitecture designed by [[Intel]] for an array of server and client products, including {{\\|Ice Lake (Client)}}, {{\\|Ice Lake (Server)}}, {{\\|Lakefield}}, and the Nervana {{nervana|NNP-I}}. The microarchitecture was developed by Intel's R&D Center (IDC) in Haifa, Israel. | ||
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** LSD can detect up to 70 µOP loops (up from 64) | ** LSD can detect up to 70 µOP loops (up from 64) | ||
* Back-end | * Back-end | ||
− | ** Wider allocation (6-way, up from 5-way in skylake and 4-way in broadwell) | + | ** Wider allocation (6-way, up from 5-way in skylake and 4-way in broadwell ) |
− | |||
** Wider decoding width with an additional simple decoder is added (from 3 simple + 1 complex in skylake’s 4 way wide decoder to 4 simple + 1 complex in Sunny cove 5 way wide decoder) | ** Wider decoding width with an additional simple decoder is added (from 3 simple + 1 complex in skylake’s 4 way wide decoder to 4 simple + 1 complex in Sunny cove 5 way wide decoder) | ||
** 1.6x larger ROB (352, up from 224 entries) | ** 1.6x larger ROB (352, up from 224 entries) |
Facts about "Sunny Cove - Microarchitectures - Intel"
codename | Sunny Cove + |
core count | 2 +, 4 +, 8 +, 10 +, 12 +, 16 +, 18 +, 20 +, 24 +, 26 +, 28 +, 32 +, 36 +, 38 + and 40 + |
designer | Intel + |
first launched | 2019 + |
full page name | intel/microarchitectures/sunny cove + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Sunny Cove + |
phase-out | 2021 + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |