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=== Physical layout === | === Physical layout === | ||
− | Bellow are the [[die]] are breakdown for the [[DDR]] [[PHY]], I/O | + | Bellow are the [[die]] are breakdown for the [[DDR]] [[PHY]], I/O PHI, SA, GPU, L3$, and the core. Note that the area of the DDR and I/O PHYs for the two smaller dies have been extrapolated from sizes of the components of the quad-core die and therefore may be off by a bit. |
<gallery widths=500px heights=275px caption="Physical Layout Breakdown" style="float:right"> | <gallery widths=500px heights=275px caption="Physical Layout Breakdown" style="float:right"> |
Facts about "Sandy Bridge (client) - Microarchitectures - Intel"
codename | Sandy Bridge (client) + |
core count | 2 + and 4 + |
designer | Intel + |
first launched | September 13, 2010 + |
full page name | intel/microarchitectures/sandy bridge (client) + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Sandy Bridge (client) + |
phase-out | November 2012 + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 32 nm (0.032 μm, 3.2e-5 mm) + |