Editing intel/microarchitectures/rocket lake

{{intel title|Rocket Lake|arch}}
{{microarchitecture
|atype=APU
|name=Rocket Lake
|designer=Intel
|manufacturer=Intel
|process=14 nm
|cores=4
|cores 2=6
|cores 3=8
|type=Superscalar
|type 2=Superpipeline
|oooe=Yes
|speculative=Yes
|renaming=Yes
|stages min=14
|stages max=19
|decode=5-way
|isa=x86-64
|extension=MOVBE
|extension 2=MMX
|extension 3=SSE
|extension 4=SSE2
|extension 5=SSE3
|extension 6=SSSE3
|extension 7=SSE4.1
|extension 8=SSE4.2
|extension 9=POPCNT
|extension 10=AVX
|extension 11=AVX2
|extension 12=AES
|extension 13=PCLMUL
|extension 14=FSGSBASE
|extension 15=RDRND
|extension 16=FMA3
|extension 17=F16C
|extension 18=BMI
|extension 19=BMI2
|extension 20=VT-x
|extension 21=VT-d
|extension 22=TXT
|extension 23=TSX
|extension 24=RDSEED
|extension 25=ADCX
|extension 26=PREFETCHW
|extension 27=CLFLUSHOPT
|extension 28=XSAVE
|extension 29=SGX
|extension 30=MPX
|l1i=48 KiB
|l1i per=core
|l1i desc=8-way set associative
|l1d=32 KiB
|l1d per=core
|l1d desc=8-way set associative
|l2=512 KiB
|l2 per=core
|l2 desc=4-way set associative
|l3=2 MiB
|l3 per=core
|l3 desc=Up to 16-way set associative
|l4=128 MiB
|l4 per=package
|l4 desc=on Iris Pro GPUs only
|core name=Cypress Cove
|predecessor=Comet Lake
|predecessor link=intel/microarchitectures/comet lake
|successor=Alder Lake
|successor link=intel/microarchitectures/alder_lake
|contemporary=Tiger Lake
|contemporary link=intel/microarchitectures/tiger_lake
}}
'''Rocket Lake''' ('''RKL''') is a planned [[microarchitecture]] designed by [[Intel]] as a successor to {{\\|Comet Lake}} for desktops and high-performance mobile devices.


== Codenames ==
{| class="wikitable"
|-
! Core !! Description !! Graphics !! Target
|-
| {{intel|Rocket Lake S|l=core}} || Mainstream performance || GT2 || Desktop performance to value, AiOs, and minis
|-
| {{intel|Rocket Lake U|l=core}} || Ultra-low power|| GT2 || Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
|}

== Brands ==
Intel is expected to release Rocket Lake under 3 main brand families:

{| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;"
|-
! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | General Description !! colspan="6" | Differentiating Features
|-
! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel|Turbo Boost|TBT}} !! [[ECC]]
|-
| [[File:core i3 logo (2015).png|50px|link=intel/core_i3]] || {{intel|Core i3}} || Low-end Performance ||  || 
|-
| [[File:core i5 logo (2015).png|50px|link=intel/core_i5]] || {{intel|Core i5}} || Mid-range Performance ||  || 
|-
| [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || High-end Performance ||  || 
|}

== Release Dates ==
Rocket Lake is expected to be released in Q1 2021.

== Compatibility==
{{empty section}}
Rocket Lake will feature the same LGA1200 socket as Comet Lake. Rocket Lake is backwards compatible with [[Comet Lake]]. Rocket Lake will have new motherboards and a new 500 series chipset. Rocket Lake will not be compatible with Alder Lake.

== Compiler support ==
{| class="wikitable"
|-
! Compiler !! Arch-Specific || Arch-Favorable
|-
| [[ICC]] || <code>-march=?</code> || <code>-mtune=?</code>
|-
| [[GCC]] || <code>-march=?</code> || <code>-mtune=?</code>
|-
| [[LLVM]] || <code>-march=?</code> || <code>-mtune=?</code>
|-
| [[Visual Studio]] || <code>/arch:AVX2</code> || <code>/?</code>
|}

=== CPUID ===
{{further|intel/cpuid|l1=Intel CPUIDs}}
{| class="wikitable tc1 tc2 tc3 tc4 tc5"
! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model !! Stepping
|-
| rowspan="2" | {{intel|Rocket Lake S|S|l=core}} || 0 || 0x6 || 0xA || 0x7 || 0x0-0x1
|-
| colspan="5" | Family 6 Model 167 Stepping 0-1<br>Stepping: A0=0, B0=1
|}

== Architecture ==
=== Key changes from {{\\|Comet Lake}}===
{{future information}}
* Core
** {{\\|Skylake}} '''➡''' {{\\|Cypress Cove}}

* GPU
** {{intel|Gen 9.5|l=arch}} '''➡''' {{intel|Gen12|l=arch}} (Xe)
** 32 EUs up from 24 EUs

* Display
** [[DisplayPort]] 1.4a (from DisplayPort 1.2)
** [[HDMI]] 2.0b (from HDMI 1.4b)

* I/O
** PCIe 4.0 (from 3.0)

* Memory
** Faster memory for mainstream desktops (i.e., {{intel|Rocket Lake S|l=core}}) DDR4-3200 (from DDR4-2933)

* Chipset
** {{intel|Cannon Point|400 Series chipset|l=chipset}} → {{intel|Rocket Point|500 Series chipset|l=chipset}}
*** 2.5G Ethernet (Foxville) support
*** Integrated WiFi 6 AX201 (GiG+) support via {{intel|CNVi}}

* Packaging
** [[Die thinning]] on top-end SKUs for better heat removal

== See also ==
codename	Rocket Lake +
core count	4 +, 6 + and 8 +
designer	Intel +
first launched	March 16, 2021 +
full page name	intel/microarchitectures/rocket lake +
instance of	microarchitecture +
instruction set architecture	x86-64 +
manufacturer	Intel +
microarchitecture type	CPU +
name	Rocket Lake +
pipeline stages (max)	19 +
pipeline stages (min)	14 +
process	14 nm (0.014 μm, 1.4e-5 mm) +