Editing intel/microarchitectures/rock creek

{{intel title|Rock Creek|arch}}
{{microarchitecture
|atype=CPU
|name=Rock Creek
|designer=Intel
|manufacturer=Intel
|introduction=December 2009
|process=45 nm
|cores=48
|isa=x86
|l1i=16 KiB
|l1i per=core
|l1i desc=4-way set associative
|l1d=16 KiB
|l1d per=core
|l1d desc=4-way set associative
|l2=256 KiB
|l2 per=core
|l2 desc=4-way set associative
|l3=16 KiB
|l3 per=tile
|predecessor=Polaris
|predecessor link=intel/microarchitectures/polaris
|successor=Knights Ferry
|successor link=intel/microarchitectures/knights ferry
}}
'''Rock Creek''' or the ''' Single-Chip Cloud Computer''' ('''SCC''') was the successor to {{\\|Polaris}}, a [[45 nm]] [[many-core]] microarchitecture designed by [[intel]] for high performance computing. The SCC, like {{\\|Polaris}}, was a research project from Intel's [[Tera-scale Computing Research Program]].

== Architecture ==
{{empty section}}

== Overview ==
[[File:intel scc chip.jpg|right|thumb|SCC Chip]]
{{empty section}}

== Rock Lake ==

:[[File:rock lake platform.png|700px]]


:[[File:rock lake platform board.jpg|700px]]

== Die ==
* [[45 nm process]]
* 1 poly, 9 Metal (Cu)
* 1,300,000,000 transistors
* 26.5 mm x 21.4 mm
** 567.1 mm² die size
* 1,567 pins LGA packages
** 970 signal pins


:[[File:rock creek die 2.png|600px]]


:[[File:rock creek die.png|600px]]


:[[File:rock creek die 3.png|600px]]


:[[File:rock creek die (annotated).png|600px]]

=== Tile ===
* 48,000,000 transistors
* 3.6 mm x 5.2 mm
** 18.7 mm² silicon area


:[[File:rock creek tile 2.png|400px]]


:[[File:rock creek tile 3.png|400px]]


:[[File:rock creek tile (annotated).png|400px]]

=== Additional Shots ===
Additional die and wafer shots provided by Intel:

<gallery mode=slideshow>
File:rock creek 1.jpg
File:rock creek 2.jpg
File:rock creek 3.jpg
File:rock creek 4.jpg
</gallery>

== Bibliography ==
* [[:File:SCC Sympossium Feb212010 FINAL-A.pdf|“Single-chip Cloud Computer”. An experimental many-core processor from Intel Labs.]] Jim Held, Intel Fellow & Director. Tera-scale Computing Research. Symposium in Santa Clara. 2/12/10.

=== Documents ===
* [[:File:SCC Sympossium Dec2010 CHN final.pptx]]
* [[:File:MARC-Symposium-Nov-2010-Stefan-Lankes.pdf|First Experiences with the SCC and a Comparison with Established Architectures]]
* [[:File:RockyLakeHW.pdf|Rocky Lake Hardware (defines LEDs)]]
* [[:File:SCC Platform Overview.pdf|The SCC Platform Overview]]
* [[:File:SCCProgrammersGuide.pdf|The SCC Programmer’s Guide Revision 1.0]]
* [[:File:SCC EAS.pdf|SCC External Architecture Specification (EAS) Revision 1.1]]
codename	Rock Creek +
core count	48 +
designer	Intel +
first launched	December 2009 +
full page name	intel/microarchitectures/rock creek +
instance of	microarchitecture +
instruction set architecture	x86 +
manufacturer	Intel +
microarchitecture type	CPU +
name	Rock Creek +
process	45 nm (0.045 μm, 4.5e-5 mm) +