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| process = 350 nm | | process = 350 nm | ||
| process 2 = 250 nm | | process 2 = 250 nm | ||
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| succession = Yes | | succession = Yes | ||
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| successor 2 link = intel/microarchitectures/pentium_m | | successor 2 link = intel/microarchitectures/pentium_m | ||
}} | }} | ||
− | + | '''P6''' was the [[microarchitecture]] for [[Intel]]'s for desktops and servers as a successor to {{\\|P5}}. Introduced in 1995 and continued until 2000, P6 was fabricated using [[350 nm]] and [[250 nm]] processes. P6 was obsoleted by {{\\|NetBurst}} in late 2000. | |
− | '''P6''' was the [[microarchitecture]] for [[Intel]]'s for desktops and servers as a successor to {{\\|P5}}. Introduced in 1995 and continued until 2000, P6 was fabricated using [[350 nm]] and [[250 nm]] processes. P6 was | ||
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== Process Technology == | == Process Technology == | ||
− | P6 was manufactured on | + | P6 was manufactured on [[0.35 µm process]] initially and alter enjoyed a process shrink down to [[0.25 µm]] allowing for considerably lower voltage and higher clock speed at a smaller silicon die area. With the shrink introduced a 5th metal layer which further reduced RC delay and die area. Intel claimed channel area was reduced by 50% with the introduction of the 5th layer. The 5th layer also enabled Intel to support C4 packaging. |
{| class="wikitable" | {| class="wikitable" | ||
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| Interconnect Pitch || 880 nm || 640 nm || 0.73x | | Interconnect Pitch || 880 nm || 640 nm || 0.73x | ||
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== Die Shot == | == Die Shot == | ||
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* [[280 nm process]] [[CMOS]] | * [[280 nm process]] [[CMOS]] | ||
* 4 metal layers | * 4 metal layers | ||
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* 540-pin BGA (Ball Grid Array) | * 540-pin BGA (Ball Grid Array) | ||
[[File:intel p6 die shot.png]] | [[File:intel p6 die shot.png]] | ||
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== References == | == References == | ||
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* Brand, Adam, et al. "Intel’s 0.25 micron, 2.0 volts logic process technology." Intel Technology Journal Q 3 (1998): 1998. | * Brand, Adam, et al. "Intel’s 0.25 micron, 2.0 volts logic process technology." Intel Technology Journal Q 3 (1998): 1998. | ||
* Integrated Circuit Engineering (ICE) Corporation. "Construction Analysis Intel 266MHz 32-Bit Pentium II (Klamath) Processor"; Shared Construction Analysis (SCA) 9706-542. | * Integrated Circuit Engineering (ICE) Corporation. "Construction Analysis Intel 266MHz 32-Bit Pentium II (Klamath) Processor"; Shared Construction Analysis (SCA) 9706-542. | ||
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Facts about "P6 - Microarchitectures - Intel"
codename | P6 + |
designer | Intel + |
first launched | October 1995 + |
full page name | intel/microarchitectures/p6 + |
instance of | microarchitecture + |
instruction set architecture | x86-32 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | P6 + |
phase-out | December 2000 + |
process | 350 nm (0.35 μm, 3.5e-4 mm) + and 250 nm (0.25 μm, 2.5e-4 mm) + |