Editing intel/microarchitectures/p6

{{intel title|P6|arch}}
{{microarchitecture
| atype            = CPU
| name             = P6
| designer         = Intel
| manufacturer     = Intel
| introduction     = October, 1995
| phase-out        = December, 2000
| process          = 350 nm
| process 2        = 250 nm

| succession       = Yes
| predecessor      = P5
| predecessor link = intel/microarchitectures/p5
| successor        = NetBurst
| successor link   = intel/microarchitectures/netburst
| successor 2      = Pentium M
| successor 2 link = intel/microarchitectures/pentium_m
}}
'''P6''' was the [[microarchitecture]] for [[Intel]]'s for desktops and servers as a successor to {{\\|P5}}. Introduced in 1995 and continued until 2000, P6 was fabricated using [[350 nm]] and [[250 nm]] processes. P6 was obsoleted by {{\\|NetBurst}} in late 2000.


== References ==
* Schutz, J., and R. Wallace. "A 450 MHz IA32 P6 family microprocessor." Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International. IEEE, 1998.
@@ Line 9: / Line 9: @@
 | process          = 350 nm
 | process 2        = 250 nm
-|isa=x86-32
 | succession       = Yes
@@ Line 19: / Line 18: @@
 | successor 2 link = intel/microarchitectures/pentium_m
 }}
-[[File:pentium pro processor with 1m l2 cache.jpg|right|thumb|{{intel|Pentium Pro}} processor with 1M of [[L2 cache]].]]
+'''P6''' was the [[microarchitecture]] for [[Intel]]'s for desktops and servers as a successor to {{\\|P5}}. Introduced in 1995 and continued until 2000, P6 was fabricated using [[350 nm]] and [[250 nm]] processes. P6 was obsoleted by {{\\|NetBurst}} in late 2000.
-'''P6''' was the [[microarchitecture]] for [[Intel]]'s for desktops and servers as a successor to {{\\|P5}}. Introduced in 1995 and continued until 2000, P6 was fabricated using [[350 nm]] and [[250 nm]] processes. P6 was made obsolete by {{\\|NetBurst}} in late 2000.
-== Codenames ==
-{{empty section}}
-== Process Technology ==
-P6 was manufactured on the [[0.35 µm process]] initially and later enjoyed a process shrink down to [[0.25 µm]], allowing for considerably lower voltage and higher clock speed at a smaller silicon die area. The shrink introduced a 5th metal layer which further reduced RC delay and die area. Intel claimed the channel area was reduced by 50% with the introduction of the 5th layer. The 5th layer also enabled Intel to support C4 packaging.
-{| class="wikitable"
-|-
-! !! [[0.35 µm]] !! [[0.25 µm]] !! Δ
-|-
-| Contacted Gate Pitch || 550 nm || 500 nm || 0.91x
-|-
-| Interconnect Pitch || 880 nm || 640 nm || 0.73x
-|}
-== Compiler support ==
-{{empty section}}
-== Architecture ==
-{{empty section}}
-== Die Shot ==
-[[File:p6 tualatin die slide.png|thumb|right|200px|Tualatin]]
-=== {{intel|Klamath|l=core}} ===
-* [[280 nm process]] [[CMOS]]
-* 4 metal layers
-* 7,500,000 transistors
-* 13.3 mm x 14.6 mm
-* 194.8 mm² die size
-*  540-pin BGA (Ball Grid Array)
-[[File:intel p6 die shot.png]]
-=== Pentium Pro ===
-* [[0.35 µm process]]
-* 5,500,000 transistors
-[[File:pentium pro die shot.png|700px]]
 == References ==
 * Schutz, J., and R. Wallace. "A 450 MHz IA32 P6 family microprocessor." Solid-State Circuits Conference, 1998. Digest of Technical Papers. 1998 IEEE International. IEEE, 1998.
-* Brand, Adam, et al. "Intel’s 0.25 micron, 2.0 volts logic process technology." Intel Technology Journal Q 3 (1998): 1998.
-* Integrated Circuit Engineering (ICE) Corporation. "Construction Analysis Intel 266MHz 32-Bit Pentium II (Klamath) Processor"; Shared Construction Analysis (SCA) 9706-542.
-== Documents ==
-* [[:File:24281603.pdf|Intel Architecture Optimization Manual]], Document 242816-003; 1997
codename	P6 +
designer	Intel +
first launched	October 1995 +
full page name	intel/microarchitectures/p6 +
instance of	microarchitecture +
instruction set architecture	x86-32 +
manufacturer	Intel +
microarchitecture type	CPU +
name	P6 +
phase-out	December 2000 +
process	350 nm (0.35 μm, 3.5e-4 mm) + and 250 nm (0.25 μm, 2.5e-4 mm) +